3d823572cc
* Initial plan * Fix nonconstant index error by using unpacked structs and arrays Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add comprehensive tests for Questa compatibility with instance arrays Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add intermediate signals for interface array fanin to fix Questa compatibility Questa simulator rejects indexing interface arrays with non-constant variables in procedural blocks (always_comb). This fix creates intermediate unpacked array signals that are assigned from interface arrays using generate loops (with genvar), then references those intermediates in the fanin logic. Changes: - Added fanin_intermediate_gen.py to generate intermediate signals - Modified APB3/APB4/AXI4-Lite cpuif classes to use intermediates for interface arrays - Updated templates to include intermediate signal section - Intermediate signals use genvar indexing (legal) instead of variable indexing (illegal in Questa) Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Fix type checking and formatting issues in fanin intermediate generator - Added proper null checks for node.array_dimensions to avoid type errors - Used getattr() to safely access is_interface and _interface attributes - Added early returns when interface is None to prevent errors - Fixed formatting issues in fanin_intermediate_gen.py - All type checks now pass (only pre-existing errors remain in other files) - All 67 tests still pass Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Fix test collection when cocotb is not installed The cocotb test files (test_runner.py) have imports that fail at module level when cocotb is not installed, causing pytest collection to fail. This prevents running tests in environments without cocotb dependencies. Solution: Updated conftest.py to conditionally ignore cocotb tests when cocotb is not available, allowing tests to pass in both environments (with and without cocotb). - When cocotb is available: only ignore test_register_access.py files (existing behavior) - When cocotb is not available: ignore all files under cocotb/** directories This allows CI to run all 67 non-simulation tests successfully without requiring cocotb/verilator dependencies for basic testing. Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * add default for unpacked struct * cocotb is test dependancy * Refactor fanin intermediate signal logic to cpuif level Moved the interface-specific signal assignment logic from fanin_intermediate_gen.py to individual cpuif classes (APB3Cpuif, APB4Cpuif, AXI4LiteCpuif). This follows better architecture principles where each cpuif knows which signals it needs. Changes: - Added fanin_intermediate_assignments() method to BaseCpuif - Implemented fanin_intermediate_assignments() in APB3Cpuif, APB4Cpuif, and AXI4LiteCpuif - Updated FaninIntermediateGenerator to call the cpuif method instead of checking interface type - Removed interface type checking logic from fanin_intermediate_gen.py This makes the code more maintainable and follows the single responsibility principle - each cpuif class knows its own signal requirements. Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>
85 lines
3.6 KiB
Python
85 lines
3.6 KiB
Python
"""AXI4-Lite-specific interface implementations."""
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from systemrdl.node import AddressableNode
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from ..interface import FlatInterface, SVInterface
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class AXI4LiteSVInterface(SVInterface):
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"""AXI4-Lite SystemVerilog interface."""
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def get_interface_type(self) -> str:
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return "axi4lite_intf"
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def get_slave_name(self) -> str:
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return "s_axil"
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def get_master_prefix(self) -> str:
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return "m_axil_"
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class AXI4LiteFlatInterface(FlatInterface):
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"""AXI4-Lite flat signal interface."""
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def get_slave_prefix(self) -> str:
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return "s_axil_"
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def get_master_prefix(self) -> str:
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return "m_axil_"
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def _get_slave_port_declarations(self, slave_prefix: str) -> list[str]:
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return [
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# Write address channel
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f"input logic {slave_prefix}AWVALID",
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f"output logic {slave_prefix}AWREADY",
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f"input logic [{self.cpuif.addr_width - 1}:0] {slave_prefix}AWADDR",
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f"input logic [2:0] {slave_prefix}AWPROT",
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# Write data channel
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f"input logic {slave_prefix}WVALID",
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f"output logic {slave_prefix}WREADY",
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f"input logic [{self.cpuif.data_width - 1}:0] {slave_prefix}WDATA",
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f"input logic [{self.cpuif.data_width // 8 - 1}:0] {slave_prefix}WSTRB",
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# Write response channel
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f"output logic {slave_prefix}BVALID",
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f"input logic {slave_prefix}BREADY",
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f"output logic [1:0] {slave_prefix}BRESP",
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# Read address channel
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f"input logic {slave_prefix}ARVALID",
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f"output logic {slave_prefix}ARREADY",
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f"input logic [{self.cpuif.addr_width - 1}:0] {slave_prefix}ARADDR",
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f"input logic [2:0] {slave_prefix}ARPROT",
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# Read data channel
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f"output logic {slave_prefix}RVALID",
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f"input logic {slave_prefix}RREADY",
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f"output logic [{self.cpuif.data_width - 1}:0] {slave_prefix}RDATA",
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f"output logic [1:0] {slave_prefix}RRESP",
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]
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def _get_master_port_declarations(self, child: AddressableNode, master_prefix: str) -> list[str]:
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return [
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# Write address channel
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f"output logic {self.signal('AWVALID', child)}",
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f"input logic {self.signal('AWREADY', child)}",
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f"output logic [{self.cpuif.addr_width - 1}:0] {self.signal('AWADDR', child)}",
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f"output logic [2:0] {self.signal('AWPROT', child)}",
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# Write data channel
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f"output logic {self.signal('WVALID', child)}",
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f"input logic {self.signal('WREADY', child)}",
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f"output logic [{self.cpuif.data_width - 1}:0] {self.signal('WDATA', child)}",
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f"output logic [{self.cpuif.data_width // 8 - 1}:0] {self.signal('WSTRB', child)}",
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# Write response channel
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f"input logic {self.signal('BVALID', child)}",
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f"output logic {self.signal('BREADY', child)}",
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f"input logic [1:0] {self.signal('BRESP', child)}",
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# Read address channel
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f"output logic {self.signal('ARVALID', child)}",
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f"input logic {self.signal('ARREADY', child)}",
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f"output logic [{self.cpuif.addr_width - 1}:0] {self.signal('ARADDR', child)}",
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f"output logic [2:0] {self.signal('ARPROT', child)}",
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# Read data channel
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f"input logic {self.signal('RVALID', child)}",
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f"output logic {self.signal('RREADY', child)}",
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f"input logic [{self.cpuif.data_width - 1}:0] {self.signal('RDATA', child)}",
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f"input logic [1:0] {self.signal('RRESP', child)}",
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]
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