d7481e71ba
* Initial plan * Fix max_decode_depth to properly control decoder hierarchy and port generation Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Fix test that relied on old depth behavior Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Update documentation for max_decode_depth parameter Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * fix format * Add variable_depth RDL file and smoke tests for max_decode_depth parameter Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add variable depth tests for APB3 and AXI4-Lite CPUIFs Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * fix * fix * bump --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>
132 lines
3.6 KiB
Python
132 lines
3.6 KiB
Python
"""Pytest wrapper launching the APB4 cocotb smoke test for variable depth."""
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from pathlib import Path
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import pytest
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from peakrdl_busdecoder.cpuif.apb4.apb4_cpuif_flat import APB4CpuifFlat
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try: # pragma: no cover - optional dependency shim
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from cocotb.runner import get_runner
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except ImportError: # pragma: no cover
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from cocotb_tools.runner import get_runner
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from tests.cocotb_lib.utils import compile_rdl_and_export, get_verilog_sources
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@pytest.mark.simulation
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@pytest.mark.verilator
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def test_apb4_variable_depth_1(tmp_path: Path) -> None:
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"""Test APB4 design with max_decode_depth=1."""
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repo_root = Path(__file__).resolve().parents[4]
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module_path, package_path = compile_rdl_and_export(
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str(repo_root / "tests" / "cocotb_lib" / "variable_depth.rdl"),
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"variable_depth",
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tmp_path,
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cpuif_cls=APB4CpuifFlat,
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max_decode_depth=1,
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)
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sources = get_verilog_sources(
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module_path,
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package_path,
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[repo_root / "hdl-src" / "apb4_intf.sv"],
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)
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runner = get_runner("verilator")
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build_dir = tmp_path / "sim_build"
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runner.build(
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sources=sources,
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hdl_toplevel=module_path.stem,
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build_dir=build_dir,
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log_file=str(tmp_path / "build_depth_1.log"),
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)
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runner.test(
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hdl_toplevel=module_path.stem,
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test_module="tests.cocotb.apb4.smoke.test_variable_depth",
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build_dir=build_dir,
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log_file=str(tmp_path / "sim_depth1.log"),
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testcase="test_depth_1",
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)
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@pytest.mark.simulation
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@pytest.mark.verilator
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def test_apb4_variable_depth_2(tmp_path: Path) -> None:
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"""Test APB4 design with max_decode_depth=2."""
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repo_root = Path(__file__).resolve().parents[4]
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module_path, package_path = compile_rdl_and_export(
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str(repo_root / "tests" / "cocotb_lib" / "variable_depth.rdl"),
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"variable_depth",
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tmp_path,
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cpuif_cls=APB4CpuifFlat,
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max_decode_depth=2,
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)
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sources = get_verilog_sources(
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module_path,
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package_path,
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[repo_root / "hdl-src" / "apb4_intf.sv"],
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)
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runner = get_runner("verilator")
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build_dir = tmp_path / "sim_build"
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runner.build(
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sources=sources,
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hdl_toplevel=module_path.stem,
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build_dir=build_dir,
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log_file=str(tmp_path / "build_depth_2.log"),
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)
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runner.test(
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hdl_toplevel=module_path.stem,
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test_module="tests.cocotb.apb4.smoke.test_variable_depth",
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build_dir=build_dir,
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log_file=str(tmp_path / "sim_depth_2.log"),
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testcase="test_depth_2",
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)
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@pytest.mark.simulation
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@pytest.mark.verilator
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def test_apb4_variable_depth_0(tmp_path: Path) -> None:
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"""Test APB4 design with max_decode_depth=0 (all levels)."""
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repo_root = Path(__file__).resolve().parents[4]
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module_path, package_path = compile_rdl_and_export(
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str(repo_root / "tests" / "cocotb_lib" / "variable_depth.rdl"),
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"variable_depth",
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tmp_path,
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cpuif_cls=APB4CpuifFlat,
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max_decode_depth=0,
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)
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sources = get_verilog_sources(
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module_path,
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package_path,
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[repo_root / "hdl-src" / "apb4_intf.sv"],
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)
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runner = get_runner("verilator")
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build_dir = tmp_path / "sim_build"
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runner.build(
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sources=sources,
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hdl_toplevel=module_path.stem,
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build_dir=build_dir,
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log_file=str(tmp_path / "build_depth_0.log"),
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)
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runner.test(
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hdl_toplevel=module_path.stem,
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test_module="tests.cocotb.apb4.smoke.test_variable_depth",
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build_dir=build_dir,
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log_file=str(tmp_path / "sim_depth_0.log"),
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testcase="test_depth_0",
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)
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