59 lines
2.2 KiB
Python
59 lines
2.2 KiB
Python
from systemrdl.node import AddressableNode
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from ...utils import get_indexed_path
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from ..base_cpuif import BaseCpuif
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class APB3Cpuif(BaseCpuif):
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template_path = "apb3_tmpl.sv"
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is_interface = True
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def _port_declaration(self, child: AddressableNode) -> str:
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base = f"apb3_intf.master m_apb_{child.inst_name}"
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if not child.is_array:
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return base
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if child.current_idx is not None:
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return f"{base}_{'_'.join(map(str, child.current_idx))}"
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return f"{base} [N_{child.inst_name.upper()}S]"
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@property
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def port_declaration(self) -> str:
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slave_ports: list[str] = ["apb3_intf.slave s_apb"]
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master_ports: list[str] = list(map(self._port_declaration, self.addressable_children))
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return ",\n".join(slave_ports + master_ports)
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def signal(
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self,
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signal: str,
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node: AddressableNode | None = None,
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) -> str:
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if node is None:
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# Node is none, so this is a slave signal
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return f"s_apb.{signal}"
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# Master signal
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return f"m_apb_{node.inst_name}.{signal}"
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def fanout(self, node: AddressableNode, idx: str | None = None) -> str:
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fanout: dict[str, str] = {}
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fanout[self.signal("PSEL", node, idx)] = (
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f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node)}|cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node)}"
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)
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fanout[self.signal("PSEL", node, idx)] = self.signal("PSEL")
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fanout[self.signal("PWRITE", node, idx)] = (
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f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node)}"
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)
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fanout[self.signal("PADDR", node, idx)] = self.signal("PADDR")
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fanout[self.signal("PWDATA", node, idx)] = "cpuif_wr_data"
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return "\n".join(map(lambda kv: f"assign {kv[0]} = {kv[1]};", fanout.items()))
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def fanin(self, node: AddressableNode, idx: str | None = None) -> str:
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fanin: dict[str, str] = {}
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fanin["cpuif_rd_data"] = self.signal("PRDATA", node, idx)
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fanin["cpuif_rd_ack"] = self.signal("PREADY", node, idx)
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fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, idx)
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return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
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