34 lines
1.1 KiB
ReStructuredText
34 lines
1.1 KiB
ReStructuredText
.. _cpuif_axi4lite:
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AMBA AXI4-Lite
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==============
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Implements the bus decoder using an
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`AMBA AXI4-Lite <https://developer.arm.com/documentation/ihi0022/e/AMBA-AXI4-Lite-Interface-Specification>`_
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CPU interface.
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The AXI4-Lite CPU interface comes in two i/o port flavors:
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SystemVerilog Interface
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* Command line: ``--cpuif axi4-lite``
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* Interface Definition: :download:`axi4lite_intf.sv <../../hdl-src/axi4lite_intf.sv>`
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* Class: :class:`peakrdl_busdecoder.cpuif.axi4lite.AXI4LiteCpuif`
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Flattened inputs/outputs
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Flattens the interface into discrete input and output ports.
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* Command line: ``--cpuif axi4-lite-flat``
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* Class: :class:`peakrdl_busdecoder.cpuif.axi4lite.AXI4LiteCpuifFlat`
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Protocol Notes
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--------------
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The AXI4-Lite adapter is intentionally simplified:
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* AW and W channels must be asserted together for writes. The adapter does not
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support decoupled address/data for writes.
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* Only a single outstanding transaction is supported. Masters should wait for
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the corresponding response before issuing the next request.
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* Burst transfers are not supported (single-beat transfers only), consistent
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with AXI4-Lite.
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