48 lines
1.5 KiB
ReStructuredText
48 lines
1.5 KiB
ReStructuredText
Known Limitations
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=================
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The busdecoder exporter intentionally focuses on address decode and routing.
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Some SystemRDL features are ignored, and a few are explicitly disallowed.
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Address Alignment
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-----------------
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All address offsets and array strides must be aligned to the CPU interface data
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bus width (in bytes). Misaligned offsets/strides are rejected.
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Wide Registers
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--------------
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If a register is wider than its ``accesswidth`` (a multi-word register), its
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``accesswidth`` must match the CPU interface data width. Multi-word registers
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with a smaller accesswidth are not supported.
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Fields Spanning Sub-Words
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-------------------------
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If a field spans multiple sub-words of a wide register:
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* Software-writable fields must have write buffering enabled
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* Fields with ``onread`` side-effects must have read buffering enabled
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These rules are enforced to avoid ambiguous multi-word access behavior.
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External Boundary References
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----------------------------
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Property references are not allowed to cross the internal/external boundary of
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the exported addrmap. References must point to components that are internal to
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the busdecoder being generated.
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CPU Interface Reset Location
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----------------------------
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Only ``cpuif_reset`` signals instantiated at the top-level addrmap (or above)
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are honored. Nested ``cpuif_reset`` signals are ignored.
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Unsupported Properties
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----------------------
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The following SystemRDL properties are explicitly rejected:
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* ``sharedextbus`` on addrmap/regfile components
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