41 lines
1.9 KiB
Systemverilog
41 lines
1.9 KiB
Systemverilog
{%- if cpuif.is_interface %}
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`ifndef SYNTHESIS
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initial begin
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assert_bad_addr_width: assert($bits({{cpuif.signal("PADDR")}}) >= {{ds.package_name}}::{{ds.module_name|upper}}_MIN_ADDR_WIDTH)
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else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits({{cpuif.signal("PADDR")}}), {{ds.package_name}}::{{ds.module_name|upper}}_MIN_ADDR_WIDTH);
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assert_bad_data_width: assert($bits({{cpuif.signal("PWDATA")}}) == {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH)
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else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("PWDATA")}}), {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH);
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end
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`endif
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{% endif -%}
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assign cpuif_req = {{cpuif.signal("PSEL")}};
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assign cpuif_wr_en = {{cpuif.signal("PWRITE")}};
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assign cpuif_rd_en = !{{cpuif.signal("PWRITE")}};
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assign cpuif_wr_addr = {{cpuif.signal("PADDR")}};
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assign cpuif_rd_addr = {{cpuif.signal("PADDR")}};
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assign cpuif_wr_data = {{cpuif.signal("PWDATA")}};
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assign {{cpuif.signal("PRDATA")}} = cpuif_rd_data;
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assign {{cpuif.signal("PREADY")}} = cpuif_rd_ack | cpuif_wr_ack;
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assign {{cpuif.signal("PSLVERR")}} = cpuif_rd_err | cpuif_wr_err;
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//--------------------------------------------------------------------------
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// Fanout CPU Bus interface signals
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//--------------------------------------------------------------------------
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{{fanout|walk(cpuif=cpuif)}}
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{%- if cpuif.is_interface %}
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//--------------------------------------------------------------------------
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// Intermediate signals for interface array fanin
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//--------------------------------------------------------------------------
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{{fanin_intermediate|walk(cpuif=cpuif)}}
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{%- endif %}
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//--------------------------------------------------------------------------
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// Fanin CPU Bus interface signals
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//--------------------------------------------------------------------------
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{{fanin|walk(cpuif=cpuif)}}
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