Create project

tests/testcases/basic.rdl

@@ -0,0 +1,58 @@
+addrmap basic {
+
+    reg {
+        default sw = rw;
+        default hw = r;
+        field {} basicfield_a[31:0];
+    } basicreg_a;
+
+    reg {
+        default sw = rw;
+        default hw = r;
+        field { sw = r; } basicfield_b[31:16];
+        field {} basicfield_c[15:0];
+    } basicreg_b;
+
+    reg {
+        default sw = r;
+        default hw = r;
+        field { fieldwidth=1;  } basicfield_d[0:0];
+        field {  } basicfield_e[2:1];
+
+    } basicreg_c;
+
+    reg {
+        default sw = w;
+        default hw = r;
+        field { fieldwidth=1;  } basicfield_f[0:0];
+        field {  } basicfield_g[2:1];
+        field {  } case[5:4]; // collide with C keyword
+
+    } basicreg_d;
+
+    reg {
+        default sw = rw;
+        default hw = r;
+        field { fieldwidth=8; } basicfield_h;
+        field { fieldwidth=8; } basicfield_i;
+        field { fieldwidth=8; } basicfield_j;
+        field { fieldwidth=8; } basicfield_k;
+    } basicreg_e;
+
+    reg {
+        default sw = rw;
+        default hw = r;
+        field { fieldwidth=8; sw = w; } basicfield_l;
+        field { fieldwidth=8; } basicfield_m;
+        field { fieldwidth=8; sw = w; } basicfield_n;
+    } basicreg_f;
+
+    reg {
+        default sw = rw;
+        default hw = r;
+        field { fieldwidth=8; sw = r; } basicfield_p;
+        field { fieldwidth=8; } basicfield_1;
+        field { fieldwidth=8; sw = r; } basicfield_r;
+    } basicreg_g;
+
+};

tests/testcases/global_type_names.rdl

@@ -0,0 +1,29 @@
+reg r_global {
+    field {} f1[4];
+
+    field myfield {};
+    myfield f2;
+    myfield f3[4];
+    field myfield2 {fieldwidth = 4;};
+    myfield2 f4;
+};
+
+regfile rf_global #(
+    longint unsigned NUM = 4
+){
+    reg r_local {
+        field {} f_param[NUM];
+        field myfield {};
+        myfield f_param2[NUM];
+    } r1;
+    r_global r2;
+
+    signal {} xyz;
+};
+
+addrmap top {
+    rf_global rf1;
+    rf_global #(.NUM (8)) rf2;
+    rf_global rf3[4] @ 0x1000 += 0x100;
+    rf_global rf4[4] @ 0x2000 += 0x200;
+};

tests/testcases/overlapping.rdl

@@ -0,0 +1,24 @@
+addrmap top {
+    reg {
+        field f_rw {sw=rw; hw=r;};
+        field f_r {sw=r; hw=w;};
+        field f_w {sw=w; hw=r;};
+
+        f_rw f1[0:0] = 0;
+        f_r f2[1:1];
+        f_w f3[1:1];
+    } overlap_fields;
+
+    reg r_rw {
+        field {sw=rw; hw=r;} f[8];
+    };
+    reg r_r {
+        field {sw=r; hw=w;} f[8];
+    };
+    reg r_w {
+        field {sw=w; hw=r;} f[8];
+    };
+    r_rw r1 @ 0x10;
+    r_r r2 @ 0x14;
+    r_w r3 @ 0x14;
+};

tests/testcases/wide_regs.rdl

@@ -0,0 +1,23 @@
+mem mem_empty #(
+    longint WIDTH = 32
+){
+    memwidth = WIDTH;
+    mementries = 16;
+};
+
+
+addrmap top {
+    reg wide_reg {
+        regwidth = 128;
+        field {} f1[32];
+        field {} f2[32];
+        field {} f3[32];
+        field {} f4[32];
+    };
+
+    wide_reg r1;
+    wide_reg r2[4];
+    wide_reg r3;
+
+    external mem_empty #(.WIDTH(128)) mem_empty_128;
+};

tests/testcases/widths_and_mem.rdl

@@ -0,0 +1,77 @@
+regfile rf1 #(
+    longint WIDTH = 32
+){
+    default regwidth = WIDTH;
+    reg myreg1 {
+        field {} f1[WIDTH/4];
+        field {} f2[WIDTH/4];
+        field {} f3[WIDTH/4];
+        field {} f4[WIDTH/4];
+    };
+    reg myreg2 {
+        field {} f1[WIDTH/8];
+        field {} f2[WIDTH/8];
+        field {} f3[WIDTH/8];
+        field {} f4[WIDTH/8];
+    };
+    reg myreg3 {
+        field {} f1[1:1];
+        field {} f2[4:3] = 3;
+        field {} f3[6:5] = 2;
+    };
+
+    myreg1 r1 @ 0x100;
+    myreg2 r2[3];
+    myreg3 r3[5];
+
+    myreg1 r4 @ 0x200;
+    myreg2 r5;
+    myreg3 r6;
+};
+
+
+mem mem_empty #(
+    longint WIDTH = 32
+){
+    memwidth = WIDTH;
+    mementries = 16;
+};
+
+mem mem_vregs #(
+    longint WIDTH = 32
+){
+    memwidth = WIDTH;
+    mementries = 16;
+    reg myreg {
+        regwidth = WIDTH;
+        field {} f1[WIDTH/2];
+        field {} f2[WIDTH/4];
+        field {} f3[WIDTH/8];
+        field {} f4[WIDTH/8];
+    };
+    myreg r1[8];
+    myreg r2;
+    myreg r3[6];
+    myreg r4;
+};
+
+
+addrmap top {
+    rf1 #(.WIDTH(8)) rf1_8;
+    rf1 #(.WIDTH(16)) rf1_16;
+    rf1 #(.WIDTH(32)) rf1_32;
+    rf1 #(.WIDTH(64)) rf1_64;
+    rf1 #(.WIDTH(8)) rf1_8_again;
+
+    external mem_empty #(.WIDTH(8)) mem_empty_8;
+    external mem_empty #(.WIDTH(16)) mem_empty_16;
+    external mem_empty #(.WIDTH(32)) mem_empty_32;
+    external mem_empty #(.WIDTH(64)) mem_empty_64;
+    external mem_empty #(.WIDTH(8)) mem_empty_8_again;
+
+    external mem_vregs #(.WIDTH(8)) mem_vregs_8;
+    external mem_vregs #(.WIDTH(16)) mem_vregs_16;
+    external mem_vregs #(.WIDTH(32)) mem_vregs_32;
+    external mem_vregs #(.WIDTH(64)) mem_vregs_64;
+    external mem_vregs #(.WIDTH(8)) mem_vregs_8_again;
+};