Add option to use xilinx simulator in tests. Not recommended - simulator is pretty awful

test/lib/regblock_testcase.py

@@ -3,7 +3,6 @@ import unittest
 import os
 import glob
 import shutil
-import subprocess
 import inspect
 import pathlib
 
@@ -17,6 +16,8 @@ from peakrdl.regblock import RegblockExporter
 from .cpuifs.base import CpuifTestMode
 from .cpuifs.apb3 import APB3
 
+from .simulators.modelsim import ModelSim
+
 
 class RegblockTestCase(unittest.TestCase):
     #: Path to the testcase's RDL file.
@@ -41,6 +42,8 @@ class RegblockTestCase(unittest.TestCase):
     #: Abort test if it exceeds this number of clock cycles
     timeout_clk_cycles = 1000
 
+    simulator_cls = ModelSim
+
     #: this gets auto-loaded via the _load_request autouse fixture
     request = None # type: pytest.FixtureRequest
 
@@ -134,43 +137,6 @@ class RegblockTestCase(unittest.TestCase):
         stream.dump(output_path)
 
 
-    @classmethod
-    def _compile_tb(cls):
-        # CD into the build directory
-        cwd = os.getcwd()
-        os.chdir(cls.get_build_dir())
-
-        cmd = [
-            "vlog", "-sv", "-quiet", "-l", "build.log",
-
-            # Free version of ModelSim throws errors if generate/endgenerate
-            # blocks are not used.
-            # These have been made optional long ago. Modern versions of SystemVerilog do
-            # not require them and I prefer not to add them.
-            "-suppress", "2720",
-
-            # Ignore noisy warning about vopt-time checking of always_comb/always_latch
-            "-suppress", "2583",
-        ]
-
-        # Add CPUIF sources
-        cmd.extend(cls.cpuif.get_tb_files())
-
-        # Add DUT sources
-        cmd.append("regblock_pkg.sv")
-        cmd.append("regblock.sv")
-
-        # Add TB
-        cmd.append("tb.sv")
-
-        # Run command!
-        try:
-            subprocess.run(cmd, check=True)
-        finally:
-            # cd back
-            os.chdir(cwd)
-
-
     @classmethod
     def setUpClass(cls):
         # Create fresh build dir
@@ -187,7 +153,16 @@ class RegblockTestCase(unittest.TestCase):
         # Create testbench from template
         cls._generate_tb(exporter)
 
-        cls._compile_tb()
+        simulator = cls.simulator_cls(testcase_cls=cls)
+
+        # cd into the build directory
+        cwd = os.getcwd()
+        os.chdir(cls.get_build_dir())
+        try:
+            simulator.compile()
+        finally:
+            # cd back
+            os.chdir(cwd)
 
 
     def setUp(self) -> None:
@@ -197,27 +172,8 @@ class RegblockTestCase(unittest.TestCase):
 
 
     def run_test(self, plusargs:List[str] = None) -> None:
-        plusargs = plusargs or []
-
-        test_name = self.request.node.name
-
-        # call vsim
-        cmd = [
-            "vsim", "-quiet",
-            "-msgmode", "both",
-            "-do", "set WildcardFilter [lsearch -not -all -inline $WildcardFilter Memory]",
-            "-do", "log -r /*;",
-            "-do", "run -all; exit;",
-            "-c",
-            "-l", "%s.log" % test_name,
-            "-wlf", "%s.wlf" % test_name,
-            "tb",
-        ]
-        for plusarg in plusargs:
-            cmd.append("+" + plusarg)
-        subprocess.run(cmd, check=True)
-
-        self.assertSimLogPass("%s.log" % test_name)
+        simulator = self.simulator_cls(testcase_cls_inst=self)
+        simulator.run(plusargs)
 
 
     def tearDown(self) -> None:

test/lib/simulators/__init__.py

@@ -0,0 +1,26 @@
+from typing import Type, TYPE_CHECKING, List
+
+if TYPE_CHECKING:
+    from ..regblock_testcase import RegblockTestCase
+
+class Simulator:
+
+    def __init__(self, testcase_cls: 'Type[RegblockTestCase]' = None, testcase_cls_inst: 'RegblockTestCase' = None) -> None:
+        self.testcase_cls = testcase_cls
+        self.testcase_cls_inst = testcase_cls_inst
+
+    @property
+    def tb_files(self) -> List[str]:
+        files = []
+        files.extend(self.testcase_cls.cpuif.get_tb_files())
+        files.append("regblock_pkg.sv")
+        files.append("regblock.sv")
+        files.append("tb.sv")
+
+        return files
+
+    def compile(self) -> None:
+        raise NotImplementedError
+
+    def run(self, plusargs:List[str] = None) -> None:
+        raise NotImplementedError

test/lib/simulators/modelsim.py

@@ -0,0 +1,61 @@
+from typing import List
+import subprocess
+import os
+
+from . import Simulator
+
+class ModelSim(Simulator):
+    def compile(self) -> None:
+        cmd = [
+            "vlog", "-sv", "-quiet", "-l", "build.log",
+
+            # Free version of ModelSim throws errors if generate/endgenerate
+            # blocks are not used.
+            # These have been made optional long ago. Modern versions of SystemVerilog do
+            # not require them and I prefer not to add them.
+            "-suppress", "2720",
+
+            # Ignore noisy warning about vopt-time checking of always_comb/always_latch
+            "-suppress", "2583",
+        ]
+
+        # Add source files
+        cmd.extend(self.tb_files)
+
+        # Run command!
+        subprocess.run(cmd, check=True)
+
+
+    def run(self, plusargs:List[str] = None) -> None:
+        plusargs = plusargs or []
+
+        test_name = self.testcase_cls_inst.request.node.name
+
+        # call vsim
+        cmd = [
+            "vsim", "-quiet",
+            "-msgmode", "both",
+            "-do", "set WildcardFilter [lsearch -not -all -inline $WildcardFilter Memory]",
+            "-do", "log -r /*;",
+            "-do", "run -all; exit;",
+            "-c",
+            "-l", "%s.log" % test_name,
+            "-wlf", "%s.wlf" % test_name,
+            "tb",
+        ]
+        for plusarg in plusargs:
+            cmd.append("+" + plusarg)
+        subprocess.run(cmd, check=True)
+
+        self.assertSimLogPass("%s.log" % test_name)
+
+
+    def assertSimLogPass(self, path: str):
+        self.testcase_cls_inst.assertTrue(os.path.isfile(path))
+
+        with open(path, encoding="utf-8") as f:
+            for line in f:
+                if line.startswith("# ** Error"):
+                    self.testcase_cls_inst.fail(line)
+                elif line.startswith("# ** Fatal"):
+                    self.testcase_cls_inst.fail(line)

test/lib/simulators/xilinx.py

@@ -0,0 +1,60 @@
+from typing import List
+import subprocess
+import os
+
+from . import Simulator
+
+class Xilinx(Simulator):
+    """
+    Don't bother using the Xilinx simulator... Its buggy and extraordinarily slow.
+    As observed in v2021.1, clocking block assignments do not seem to actually simulate
+    correctly - assignemnt statements get ignored or the values get mangled.
+
+    Keeping this here in case someday it works better...
+    """
+    def compile(self) -> None:
+        cmd = [
+            "xvlog", "--sv"
+        ]
+        cmd.extend(self.tb_files)
+        subprocess.run(cmd, check=True)
+
+        cmd = [
+            "xelab",
+            "--timescale", "1ns/1ps",
+            "--debug", "all",
+            "tb",
+        ]
+        subprocess.run(cmd, check=True)
+
+
+    def run(self, plusargs:List[str] = None) -> None:
+        plusargs = plusargs or []
+
+        test_name = self.testcase_cls_inst.request.node.name
+
+        # call vsim
+        cmd = [
+            "xsim",
+            "--R",
+            "--log", "%s.log" % test_name,
+            "tb",
+        ]
+
+        for plusarg in plusargs:
+            cmd.append("--testplusarg")
+            cmd.append(plusarg)
+        subprocess.run(cmd, check=True)
+
+        self.assertSimLogPass("%s.log" % test_name)
+
+
+    def assertSimLogPass(self, path: str):
+        self.testcase_cls_inst.assertTrue(os.path.isfile(path))
+
+        with open(path, encoding="utf-8") as f:
+            for line in f:
+                if line.startswith("Error:"):
+                    self.testcase_cls_inst.fail(line)
+                elif line.startswith("Fatal:"):
+                    self.testcase_cls_inst.fail(line)

test/lib/templates/tb_base.sv

@@ -57,8 +57,13 @@ module tb;
 
 {%- if exporter.hwif.has_output_struct %}
     {% sv_line_anchor %}
-    initial forever begin
-        ##1; if(!rst) assert(!$isunknown({>>{hwif_out}})) else $error("hwif_out has X's!");
+    initial begin
+        logic [$bits(hwif_out)-1:0] tmp;
+        forever begin
+            ##1;
+            tmp = {>>{hwif_out}}; // Workaround for Xilinx's xsim - assign to tmp variable
+            if(!rst) assert(!$isunknown(tmp)) else $error("hwif_out has X's!");
+        end
     end
 {%- endif %}