From 06bd5677505193642148b5234bd6baab557eace8 Mon Sep 17 00:00:00 2001 From: Alex Mykyta Date: Fri, 11 Apr 2025 21:26:27 -0700 Subject: [PATCH] Increment version --- docs/index.rst | 27 ++++----------------------- src/peakrdl_regblock/__about__.py | 2 +- 2 files changed, 5 insertions(+), 24 deletions(-) diff --git a/docs/index.rst b/docs/index.rst index b3bc11a..d072dbc 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -10,35 +10,16 @@ your hardware design. * Options for many popular CPU interface protocols (AMBA APB, AXI4-Lite, and more) * Configurable pipelining options for designs with fast clock rates. * Broad support for SystemRDL 2.0 features -* Fully synthesizable SystemVerilog. Tested on Xilinx/AMD's Vivado & Intel Quartus - -.. warning:: - - The PeakRDL-regblock SV generator is still in pre-production (v0.x version numbers). - During this time, I may decide to refactor things which could affect compatibility. -Installing ----------- - -Install from `PyPi`_ using pip - -.. code-block:: bash - - python3 -m pip install peakrdl-regblock - -.. _PyPi: https://pypi.org/project/peakrdl-regblock - - - -Example -------- +Quick Start +----------- The easiest way to use PeakRDL-regblock is via the `PeakRDL command line tool `_: .. code-block:: bash - # Install the command line tool - python3 -m pip install peakrdl + # Install PeakRDL-regblock along with the command-line tool + python3 -m pip install peakrdl-regblock[cli] # Export! peakrdl regblock atxmega_spi.rdl -o regblock/ --cpuif axi4-lite diff --git a/src/peakrdl_regblock/__about__.py b/src/peakrdl_regblock/__about__.py index 9428a75..9d75964 100644 --- a/src/peakrdl_regblock/__about__.py +++ b/src/peakrdl_regblock/__about__.py @@ -1,2 +1,2 @@ -version_info = (0, 23, 0) +version_info = (1, 0, 0) __version__ = ".".join([str(n) for n in version_info])