bslathi19/PeakRDL-regblock
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Switch to LGPLv3 license

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This commit is contained in:
Alex Mykyta
2025-06-18 18:45:35 -07:00
parent 0ff68fade9
commit 08c24d4784
5 changed files with 176 additions and 685 deletions
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4
pyproject.toml
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@@ -16,7 +16,7 @@ authors = [
]
description = "Compile SystemRDL into a SystemVerilog control/status register (CSR) block"
readme = "README.md"
license = {text = "GPLv3"}
license = {text = "LGPLv3"}
keywords = [
"SystemRDL", "PeakRDL", "CSR", "compiler", "tool", "registers", "generator",
"Verilog", "SystemVerilog", "register abstraction layer",
@@ -28,7 +28,7 @@ classifiers = [
"Programming Language :: Python :: 3",
"Programming Language :: Python :: 3 :: Only",
"Intended Audience :: Developers",
"License :: OSI Approved :: GNU General Public License v3 (GPLv3)",
"License :: OSI Approved :: GNU Lesser General Public License v3 (LGPLv3)",
"Operating System :: OS Independent",
"Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
]