From 0d39774d227185a662a90db6c11f71ad162129f1 Mon Sep 17 00:00:00 2001
From: Alex Mykyta <amykyta3@users.noreply.github.com>
Date: Fri, 5 Jan 2024 20:51:19 -0800
Subject: [PATCH] Fixup whitespace

---
 src/peakrdl_regblock/__about__.py                | 2 +-
 src/peakrdl_regblock/module_tmpl.sv              | 7 ++++---
 src/peakrdl_regblock/package_tmpl.sv             | 1 +
 src/peakrdl_regblock/write_buffering/template.sv | 2 +-
 4 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/src/peakrdl_regblock/__about__.py b/src/peakrdl_regblock/__about__.py
index 11ac8e1..5f4bb0b 100644
--- a/src/peakrdl_regblock/__about__.py
+++ b/src/peakrdl_regblock/__about__.py
@@ -1 +1 @@
-__version__ = "0.19.0"
+__version__ = "0.20.0"
diff --git a/src/peakrdl_regblock/module_tmpl.sv b/src/peakrdl_regblock/module_tmpl.sv
index 632463e..45d5eaa 100644
--- a/src/peakrdl_regblock/module_tmpl.sv
+++ b/src/peakrdl_regblock/module_tmpl.sv
@@ -135,12 +135,12 @@ module {{ds.module_name}} (
     always_comb begin
     {%- if ds.has_external_addressable %}
         automatic logic is_external = '0;
-    {% endif %}
+    {%- endif %}
         {{address_decode.get_implementation()|indent(8)}}
     {%- if ds.has_external_addressable %}
         decoded_strb_is_external = is_external;
         external_req = is_external;
-    {% endif %}
+    {%- endif %}
     end
 
     // Pass down signals to next stage
@@ -251,7 +251,7 @@ module {{ds.module_name}} (
     logic readback_err;
     logic readback_done;
     logic [{{cpuif.data_width-1}}:0] readback_data;
-    {{readback_implementation|indent}}
+{{readback_implementation|indent}}
 {% if ds.retime_read_response %}
     always_ff {{get_always_ff_event(cpuif.reset)}} begin
         if({{get_resetsignal(cpuif.reset)}}) begin
@@ -283,3 +283,4 @@ module {{ds.module_name}} (
     assign cpuif_rd_err = readback_err;
 {%- endif %}
 endmodule
+{# (eof newline anchor) #}
diff --git a/src/peakrdl_regblock/package_tmpl.sv b/src/peakrdl_regblock/package_tmpl.sv
index 6a411df..1c7933b 100644
--- a/src/peakrdl_regblock/package_tmpl.sv
+++ b/src/peakrdl_regblock/package_tmpl.sv
@@ -8,3 +8,4 @@ package {{ds.package_name}};
 
     {{hwif.get_package_contents()|indent}}
 endpackage
+{# (eof newline anchor) #}
diff --git a/src/peakrdl_regblock/write_buffering/template.sv b/src/peakrdl_regblock/write_buffering/template.sv
index 7e5d0eb..78bbf46 100644
--- a/src/peakrdl_regblock/write_buffering/template.sv
+++ b/src/peakrdl_regblock/write_buffering/template.sv
@@ -24,7 +24,7 @@ always_ff {{get_always_ff_event(cpuif.reset)}} begin
             {%- endif %}
         end
         {%- endfor %}
-        {% if is_own_trigger %}
+        {%- if is_own_trigger %}
         {{wbuf_prefix}}.trigger_q <= {{wbuf.get_raw_trigger(node)}};
         {%- endif %}
     end