basic framework
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doc/logbooks/template-layers/1.1.hardware-interface
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doc/logbooks/template-layers/1.1.hardware-interface
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================================================================================
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Summary
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================================================================================
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RTL interface that provides access to per-field context signals
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Regarding signals:
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I think RDL-declared signals should actually be part of the hwif input
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structure.
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Exceptions:
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- if the signal instance is at the top-level, it will get promoted to the
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top level port list for convenience, and therefore omitted from the struct
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================================================================================
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Naming Scheme
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================================================================================
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hwif_out
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.my_regblock
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.my_reg[X][Y]
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.my_field
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.value
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.anded
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hwif_in
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.my_regblock
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.my_reg[X][Y]
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.my_field
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.value
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.we
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.my_signal
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.my_fieldreset_signal
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================================================================================
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Flattened mode? --> NO
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================================================================================
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If user wants a flattened list of ports,
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still use the same hwif_in/out struct internally.
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Rather than declaring hwif_in and hwif_out in the port list, declare it internally
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Add a mapping layer in the body of the module that performs a ton of assign statements
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to map flat signals <-> struct
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Alternatively, don't do this at all.
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If I want to add a flattened mode, generate a wrapper module instead.
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Marking this as YAGNI for now.
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================================================================================
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IO Signals
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================================================================================
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Outputs:
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field value
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If hw readable
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bitwise reductions
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if anded, ored, xored == True, output a signal
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swmod/swacc
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event strobes
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Inputs:
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field value
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If hw writable
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we/wel
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if either is boolean, and true
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not part of external hwif if reference
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mutually exclusive
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hwclr/hwset
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if either is boolean, and true
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not part of external hwif if reference
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incr/decr
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if counter=true, generate BOTH
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incrvalue/decrvalue
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if either incrwidth/decrwidth are set
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signals!
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any signal instances instantiated in the scope
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