basic framework

peakrdl/regblock/cpuif/__init__.py

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+from .base import CpuifBase

peakrdl/regblock/cpuif/apb4/__init__.py

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+from ..base import CpuifBase
+
+class APB4_Cpuif(CpuifBase):
+    template_path = "cpuif/apb4/apb4_tmpl.sv"
+
+    @property
+    def port_declaration(self) -> str:
+        return "apb4_intf.slave s_apb"
+
+    def signal(self, name:str) -> str:
+        return "s_apb." + name
+
+
+class APB4_Cpuif_flattened(APB4_Cpuif):
+    @property
+    def port_declaration(self) -> str:
+        # TODO: Reference data/addr width from verilog parameter perhaps?
+        lines = [
+            "input wire %s" % self.signal("psel"),
+            "input wire %s" % self.signal("penable"),
+            "input wire %s" % self.signal("pwrite"),
+            "input wire %s" % self.signal("pprot"),
+            "input wire [%d-1:0] %s" % (self.addr_width, self.signal("paddr")),
+            "input wire [%d-1:0] %s" % (self.data_width, self.signal("pwdata")),
+            "input wire [%d-1:0] %s" % (self.data_width / 8, self.signal("pstrb")),
+            "output logic %s" % self.signal("pready"),
+            "output logic [%d-1:0] %s" % (self.data_width, self.signal("prdata")),
+            "output logic %s" % self.signal("pslverr"),
+        ]
+        return ",\n".join(lines)
+
+    def signal(self, name:str) -> str:
+        return "s_apb_" + name

peakrdl/regblock/cpuif/apb4/apb4_tmpl.sv

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+{% extends "cpuif/base_tmpl.sv" %}
+{%- import "utils_tmpl.sv" as utils with context %}
+
+{% block body %}
+// Request
+logic is_active;
+{%- call utils.AlwaysFF(cpuif_reset) %}
+    if({{cpuif_reset.activehigh_identifier}}) begin
+        is_active <= '0;
+        cpuif_req <= '0;
+        cpuif_req_is_wr <= '0;
+        cpuif_addr <= '0;
+        cpuif_wr_data <= '0;
+        cpuif_wr_bitstrb <= '0;
+    end else begin
+        if(~is_active) begin
+            if({{cpuif.signal("psel")}}) begin
+                is_active <= '1;
+                cpuif_req <= '1;
+                cpuif_req_is_wr <= {{cpuif.signal("pwrite")}};
+                cpuif_addr <= {{cpuif.signal("paddr")}}[ADDR_WIDTH-1:0];
+                cpuif_wr_data <= {{cpuif.signal("pwdata")}};
+                for(int i=0; i<DATA_WIDTH/8; i++) begin
+                    cpuif_wr_bitstrb[i*8 +: 8] <= {{"{8{"}}{{cpuif.signal("pstrb")}}[i]{{"}}"}};
+                end
+            end
+        end else begin
+            cpuif_req <= '0;
+            if(cpuif_rd_ack || cpuif_wr_ack) begin
+                is_active <= '0;
+            end
+        end
+    end
+{%- endcall %}
+
+// Response
+assign {{cpuif.signal("pready")}} = cpuif_rd_ack | cpuif_wr_ack;
+assign {{cpuif.signal("prdata")}} = cpuif_rd_data;
+assign {{cpuif.signal("pslverr")}} = cpuif_rd_err | cpuif_wr_err;
+{%- endblock body%}

peakrdl/regblock/cpuif/base.py

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+from typing import TYPE_CHECKING
+
+import jinja2
+
+if TYPE_CHECKING:
+    from ..exporter import RegblockExporter
+    from ..signals import SignalBase
+
+class CpuifBase:
+    template_path = "cpuif/base_tmpl.sv"
+
+    def __init__(self, exporter:'RegblockExporter', cpuif_reset:'SignalBase', data_width:int=32, addr_width:int=32):
+        self.exporter = exporter
+        self.cpuif_reset = cpuif_reset
+        self.data_width = data_width
+        self.addr_width = addr_width
+
+    @property
+    def port_declaration(self) -> str:
+        raise NotImplementedError()
+
+    def get_implementation(self) -> str:
+        context = {
+            "cpuif": self,
+            "cpuif_reset": self.cpuif_reset,
+            "data_width": self.data_width,
+            "addr_width": self.addr_width,
+        }
+
+        template = self.exporter.jj_env.get_template(self.template_path)
+        return template.render(context)

peakrdl/regblock/cpuif/base_tmpl.sv

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+begin
+    {%- filter indent %}
+    {%- block body %}
+    {%- endblock %}
+    {%- endfilter %}
+end