Add support for field paritycheck. #35

tests/lib/tb_base.sv

@@ -26,6 +26,11 @@ module tb;
     regblock_pkg::regblock__out_t hwif_out;
 {%- endif %}
 
+{%- if exporter.ds.has_paritycheck %}
+    logic parity_error;
+{%- endif %}
+
+
 {%- block declarations %}
 {%- endblock %}
 
@@ -43,6 +48,10 @@ module tb;
         input hwif_out;
 {%- endif %}
 
+{%- if exporter.ds.has_paritycheck %}
+        input parity_error;
+{%- endif %}
+
 {%- filter indent %}
 {%- block clocking_dirs %}
 {%- endblock %}
@@ -68,6 +77,9 @@ module tb;
             ##1;
             tmp = {>>{hwif_out}}; // Workaround for Xilinx's xsim - assign to tmp variable
             if(!rst) assert(!$isunknown(tmp)) else $error("hwif_out has X's!");
+            {%- if exporter.ds.has_paritycheck %}
+            if(!rst) assert(!$isunknown(parity_error)) else $error("parity_error has X's!");
+            {%- endif %}
         end
     end
 {%- endif %}

tests/test_parity/regblock.rdl

@@ -0,0 +1,14 @@
+addrmap top {
+    default paritycheck;
+    default sw=rw;
+    default hw=na;
+
+    reg my_reg {
+        field {} f1[16] = 0;
+        field {} f2[8] = 0;
+        field {} f3 = 0;
+    };
+
+    my_reg r1 @ 0x000;
+    my_reg r2[8] @ 0x1000;
+};

tests/test_parity/tb_template.sv

@@ -0,0 +1,37 @@
+{% extends "lib/tb_base.sv" %}
+
+{% block seq %}
+    {% sv_line_anchor %}
+    ##1;
+    cb.rst <= '0;
+    ##1;
+
+    fork
+        begin
+            repeat(50) begin
+                automatic int i = $urandom_range(7,0);
+                cpuif.write('h0, $urandom());
+                cpuif.write('h1000 + i*4, $urandom());
+            end
+        end
+        begin
+            forever begin
+                assert(cb.parity_error != 1'b1);
+                @cb;
+            end
+        end
+    join_any
+    disable fork;
+
+    cpuif.write('h0, 'd0);
+    force dut.field_storage.r1.f1.value[3] = 1'b1;
+    release dut.field_storage.r1.f1.value[3];
+    @cb;
+    @cb;
+    assert(cb.parity_error == 1'b1);
+    cpuif.write('h0, 'd0);
+    @cb;
+    @cb;
+    assert(cb.parity_error == 1'b0);
+
+{% endblock %}

tests/test_parity/testcase.py

@@ -0,0 +1,5 @@
+from ..lib.sim_testcase import SimTestCase
+
+class Test(SimTestCase):
+    def test_dut(self):
+        self.run_test()