Enhance AXI4-Lite CPU Interface to support high performance pipelined transactions

2022-02-15 22:31:18 -08:00
parent d0ba488904
commit 0fa26f2030
11 changed files with 253 additions and 94 deletions
--- a/docs/architecture.rst
+++ b/docs/architecture.rst
@@ -51,4 +51,5 @@ optimally reduced.

 A second optional read response retiming register can be enabled in-line with the
 path back to the CPU interface layer. This can be useful if the CPU interface protocol
-used has a fully combinational response path, and needs to be retimed further.
+used has a fully combinational response path, and the design's complexity requires
+this path to be retimed further.
--- a/docs/cpuif/axi4lite.rst
+++ b/docs/cpuif/axi4lite.rst
@@ -0,0 +1,11 @@
+AMBA AXI4-Lite
+==============
+
+TODO: Describe the following
+
+* List of interface signals
+
+    * interface name & modports (link to advanced topics in case user wants to override)
+    * flattened equivalents
+
+* Download link to SV interface definition
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -47,6 +47,7 @@ Links

   cpuif/addressing
   cpuif/apb3
+   cpuif/axi4lite
   cpuif/advanced
   cpuif/internal_protocol