Enhance AXI4-Lite CPU Interface to support high performance pipelined transactions

2022-02-15 22:31:18 -08:00
parent d0ba488904
commit 0fa26f2030
11 changed files with 253 additions and 94 deletions
--- a/docs/architecture.rst
+++ b/docs/architecture.rst
@@ -51,4 +51,5 @@ optimally reduced.

 A second optional read response retiming register can be enabled in-line with the
 path back to the CPU interface layer. This can be useful if the CPU interface protocol
-used has a fully combinational response path, and needs to be retimed further.
+used has a fully combinational response path, and the design's complexity requires
+this path to be retimed further.