Enhance AXI4-Lite CPU Interface to support high performance pipelined transactions

2022-02-15 22:31:18 -08:00
parent d0ba488904
commit 0fa26f2030
11 changed files with 253 additions and 94 deletions
--- a/docs/cpuif/axi4lite.rst
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+AMBA AXI4-Lite
+==============
+
+TODO: Describe the following
+
+* List of interface signals
+
+    * interface name & modports (link to advanced topics in case user wants to override)
+    * flattened equivalents
+
+* Download link to SV interface definition