Enhance AXI4-Lite CPU Interface to support high performance pipelined transactions

2022-02-15 22:31:18 -08:00
parent d0ba488904
commit 0fa26f2030
11 changed files with 253 additions and 94 deletions
--- a/peakrdl/regblock/addr_decode.py
+++ b/peakrdl/regblock/addr_decode.py
@@ -87,7 +87,7 @@ class DecodeLogicGenerator(RDLForLoopGenerator):


    def enter_Reg(self, node: RegNode) -> None:
-        s = f"{self.addr_decode.get_access_strobe(node)} = cpuif_req & (cpuif_addr == {self._get_address_str(node)});"
+        s = f"{self.addr_decode.get_access_strobe(node)} = cpuif_req_masked & (cpuif_addr == {self._get_address_str(node)});"
        self.add_content(s)