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Remove green checkmarks now that most things are supported

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This commit is contained in:
Alex Mykyta
2022-11-10 19:57:11 -08:00
parent c54aa894f5
commit 10f08f7865
4 changed files with 15 additions and 141 deletions
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105
docs/props/field.rst
View File

@@ -35,12 +35,10 @@ If set, field will get cleared back to zero after being written.
sw
^^^
|OK|
All sw access modes are supported except for ``w1`` and ``rw1``.
swacc
^^^^^
|OK|
If true, infers an output signal ``hwif_out..swacc`` that is asserted when
accessed by software. Specifically, on the same clock cycle that the field is
@@ -57,7 +55,6 @@ being sampled during a software read operation, or as it is being written.
swmod
^^^^^
|OK|
If true, infers an output signal ``hwif_out..swmod`` that is asserted as the
field is being modified by software. This can be due to a software write
@@ -80,18 +77,14 @@ Provides a mechanism that allows hardware to override whether the field is
writable by software.
boolean
|OK|
If True, infers an input signal ``hwif_in..swwe`` or ``hwif_in..swwel``.
reference
|OK|
Single-bit reference controls field's behavior.
woclr/woset
^^^^^^^^^^^
|OK|
See ``onwrite``. These are effectively aliases of the onwrite property.
--------------------------------------------------------------------------------
@@ -101,16 +94,12 @@ Hardware Access Properties
anded/ored/xored
^^^^^^^^^^^^^^^^
|OK|
If true, infers the existence of output signal: ``hwif_out..anded``,
``hwif_out..ored``, ``hwif_out..xored``
hw
^^^
|OK|
Controls hardware access to the field.
If readable, enables output signal ``hwif_out..value``. If writable, enables
@@ -122,25 +111,18 @@ the inferred ``hwif_in..next`` input with an alternate reference.
hwclr/hwset
^^^^^^^^^^^
If both ``hwclr`` and ``hwset`` properties are used, and both are asserted at
the same clock cycle, then ``hwset`` will take precedence.
boolean
|OK|
If true, infers the existence of input signal: ``hwif_in..hwclr``, ``hwif_in..hwset``
reference
|OK|
Reference to any single-bit internal object to drive this control.
hwenable/hwmask
^^^^^^^^^^^^^^^
|OK|
Reference to a component that provides bit-level control of hardware writeability.
@@ -161,13 +143,9 @@ If true, infers the existence of input signal: ``hwif_in..we``, ``hwif_in..wel``
]}
boolean
|OK|
If true, infers the existence of input signal ``hwif_in..we`` or ``hwif_in..wel``
reference
|OK|
Reference to any single-bit internal object to drive this control.
--------------------------------------------------------------------------------
@@ -177,8 +155,6 @@ Counter Properties
counter
^^^^^^^
|OK|
If true, marks this field as a counter. The counter direction is inferred based
based on which properties are assigned. By default, an up-counter is implemented.
If any of the properties associated with an up-counter are used, then up-counting
@@ -192,8 +168,6 @@ of counter described.
incr
^^^^
|OK|
Assign a reference to an alternate control signal to increment the counter.
If assigned, the inferred ``hwif_in..incr`` input will not be generated.
@@ -204,24 +178,17 @@ If an alternate saturation point is specified, the counter value will be
adjusted so that it does not exceed that limit, even after non-increment actions.
boolean
|OK|
If true, saturation point is at the counter's maximum count value. (2^width - 1)
integer
|OK|
Specify a static saturation value.
reference
|OK|
Specify a dynamic saturation value.
incrthreshold/threshold
^^^^^^^^^^^^^^^^^^^^^^^
If assigned, infers a ``hwif_out..incrthreshold`` output signal. This signal is
asserted if the counter value is greater or equal to the threshold.
@@ -241,18 +208,12 @@ asserted if the counter value is greater or equal to the threshold.
boolean
|OK|
If true, threshold is the counter's maximum count value. (2^width - 1)
integer
|OK|
Specify a static threshold value.
reference
|OK|
Specify a dynamic threshold value.
@@ -261,23 +222,19 @@ incrvalue
Override the counter's increment step size.
integer
|OK|
Specify a static increment step size.
reference
|OK|
Reference a component that controls the step size.
incrwidth
^^^^^^^^^
|OK|
If assigned, infers an input signal ``hwif_in..incrvalue``. The value of this
property defines the signal's width.
overflow
^^^^^^^^
|OK|
If true, infers an output signal ``hwif_out..overflow`` that is asserted when
the counter is about to wrap.
@@ -298,8 +255,6 @@ the counter is about to wrap.
decr
^^^^
|OK|
Assign a reference to an alternate control signal to decrement the counter.
If assigned, the inferred ``hwif_in..decr`` input will not be generated.
@@ -311,18 +266,12 @@ If an alternate saturation point is specified, the counter value will be
adjusted so that it does not exceed that limit, even after non-decrement actions.
boolean
|OK|
If true, saturation point is when the counter reaches 0.
integer
|OK|
Specify a static saturation value.
reference
|OK|
Specify a dynamic saturation value.
@@ -347,18 +296,12 @@ asserted if the counter value is less than or equal to the threshold.
boolean
|OK|
If true, threshold is 0.
integer
|OK|
Specify a static threshold value.
reference
|OK|
Specify a dynamic threshold value.
@@ -367,22 +310,20 @@ decrvalue
Override the counter's decrement step size.
integer
|OK|
Specify a static step size.
reference
|OK|
Reference to a component that controls the step size.
decrwidth
^^^^^^^^^
|OK|
If assigned, infers an input signal ``hwif_in..decrvalue``. The value of this
property defines the signal's width.
underflow
^^^^^^^^^
|OK|
If true, infers an output signal ``hwif_out..underflow`` that is asserted when
the counter is about to wrap.
@@ -414,56 +355,42 @@ that an interrupt is active. This is an or-reduction of all interrupt fields
after applying the appropriate ``enable`` or ``mask`` to the field value.
level (default)
|OK|
Interrupt is level-sensitive. If a bit on the field's ``hwif_in..next`` input
is '1', it will trigger an interrupt event.
posedge
|OK|
If a bit on the field's ``hwif_in..next`` input transitions from '0' to '1',
it will trigger an interrupt event. This transition shall still be synchronous
to the register block's clock.
negedge
|OK|
If a bit on the field's ``hwif_in..next`` input transitions from '1' to '0',
it will trigger an interrupt event. This transition shall still be synchronous
to the register block's clock.
bothedge
|OK|
If a bit on the field's ``hwif_in..next`` input transitions from '0' to '1' or '1' to '0',
it will trigger an interrupt event. This transition shall still be synchronous
to the register block's clock.
nonsticky
|OK|
Interrupt event is not sticky.
enable
^^^^^^
|OK|
Reference to a field or signal that, if set to 1, define which bits in the field
are used to assert an interrupt.
mask
^^^^
|OK|
Reference to a field or signal that, if set to 1, define which bits in the field
are *not* used to assert an interrupt.
haltenable
^^^^^^^^^^
|OK|
Reference to a field or signal that, if set to 1, define which bits in the field
are used to assert the halt output.
@@ -472,8 +399,6 @@ If this property is set, the enclosing register will infer a ``hwif_out..halt``
haltmask
^^^^^^^^
|OK|
Reference to a field or signal that, if set to 1, define which bits in the field
are *not* used to assert the halt output.
@@ -482,8 +407,6 @@ If this property is set, the enclosing register will infer a ``hwif_out..halt``
stickybit
^^^^^^^^^
|OK|
When an interrupt trigger occurs, a stickybit field will set the corresponding
bit to '1' and hold it until it is cleared by a software access.
@@ -506,8 +429,6 @@ The waveform below demonstrates a level-sensitive interrupt:
sticky
^^^^^^
|OK|
Unlike ``stickybit`` fields, a sticky field will latch an entire value. The
value is latched as soon as ``hwif_in..next`` is nonzero, and is held until the
field contents are cleared back to 0 by a software access.
@@ -534,8 +455,6 @@ encode
next
^^^^
|OK|
If assigned, replaces the inferred ``hwif_in..next`` input with an explicit reference.
@@ -545,8 +464,6 @@ paritycheck
precedence
^^^^^^^^^^
|OK|
Control whether hardware or software has precedence when field value update
contention occurs. Software has precedence by default.
@@ -556,15 +473,11 @@ Control the reset value of the field's storage element.
If not specified, the field will not be reset.
integer
|OK|
Static reset value
reference
|OK|
Reference to a dynamic reset value.
resetsignal
^^^^^^^^^^^
|OK|
Provide an alternate reset trigger for this field.

5
docs/props/reg.rst
View File

@@ -6,10 +6,9 @@ Register Properties
accesswidth
-----------
|OK|
Control the software access width. The register block's CPUIF bus width is
determined by the maximum accesswidth encountered.
regwidth
--------
|OK|
Control the bit-width of the register.

35
docs/props/rhs_props.rst
View File

@@ -20,31 +20,23 @@ Field
field -> swacc
^^^^^^^^^^^^^^
|OK|
Single-cycle strobe that indicates the field is being accessed by software
(read or write).
field -> swmod
^^^^^^^^^^^^^^^
|OK|
Single-cycle strobe that indicates the field is being modified during a software
access operation.
field -> swwe/swwel
^^^^^^^^^^^^^^^^^^^
|OK|
Represents the signal that controls the field's swwe/swwel behavior.
field -> anded/ored/xored
^^^^^^^^^^^^^^^^^^^^^^^^^
|OK|
Represents the current and/or/xor reduction of the field's value.
@@ -57,8 +49,6 @@ Represents the signal that controls the field's hwclr/hwset behavior.
field -> hwenable/hwmask
^^^^^^^^^^^^^^^^^^^^^^^^
|OK|
Represents the signal that controls the field's hwenable/hwmask behavior.
field -> we/wel
@@ -86,10 +76,9 @@ Field Counter Properties
field -> incr
^^^^^^^^^^^^^
|OK|
Represents the signal that controls the field's counter increment control.
field -> incrsaturate/saturate
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|EX|
@@ -121,20 +110,14 @@ exceeded its incrthreshold.
field -> incrvalue
^^^^^^^^^^^^^^^^^^
|OK|
Represents the value that was assigned to this property.
field -> overflow
^^^^^^^^^^^^^^^^^
|OK|
Represents the event signal that is asserted when the counter is about to wrap.
field -> decr
^^^^^^^^^^^^^
|OK|
Represents the signal that controls the field's counter decrement control.
field -> decrsaturate
@@ -167,14 +150,10 @@ exceeded its incrthreshold.
field -> decrvalue
^^^^^^^^^^^^^^^^^^
|OK|
Represents the value that was assigned to this property.
field -> underflow
^^^^^^^^^^^^^^^^^^
|OK|
Represents the event signal that is asserted when the counter is about to wrap.
--------------------------------------------------------------------------------
@@ -184,26 +163,18 @@ Field Interrupt Properties
field -> enable
^^^^^^^^^^^^^^^
|OK|
Represents the value that was assigned to this property.
field -> mask
^^^^^^^^^^^^^
|OK|
Represents the value that was assigned to this property.
field -> haltenable
^^^^^^^^^^^^^^^^^^^
|OK|
Represents the value that was assigned to this property.
field -> haltmask
^^^^^^^^^^^^^^^^^
|OK|
Represents the value that was assigned to this property.
@@ -214,12 +185,8 @@ Register
reg -> intr
^^^^^^^^^^^
|OK|
References the register's ``hwif_out..intr`` signal.
reg -> halt
^^^^^^^^^^^
|OK|
References the register's ``hwif_out..halt`` signal.

11
docs/props/signal.rst
View File

@@ -7,27 +7,22 @@ Signal Properties
activehigh/activelow
--------------------
|OK|
Only relevant for signals used as resets. Defines the reset signal's polarity.
sync/async
----------
|OK|
Only supported for signals used as resets to infer edge-sensitive reset.
Ignored in all other contexts.
cpuif_reset
-----------
|OK|
Specify that this signal shall be used as alternate reset signal for the CPU
interface for this regblock.
field_reset
-----------
|OK|
Specify that this signal is used as an alternate reset signal for all fields
instantiated in sub-hierarchies relative to this signal.