bslathi19/PeakRDL-regblock
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Remove green checkmarks now that most things are supported

Browse Source
This commit is contained in:
Alex Mykyta
2022-11-10 19:57:11 -08:00
parent c54aa894f5
commit 10f08f7865
4 changed files with 15 additions and 141 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
docs/props/reg.rst
View File

@@ -6,10 +6,9 @@ Register Properties
accesswidth
-----------
|OK|
Control the software access width. The register block's CPUIF bus width is
determined by the maximum accesswidth encountered.
regwidth
--------
|OK|
Control the bit-width of the register.