bslathi19/PeakRDL-regblock
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Add missing comment for external components

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This commit is contained in:
Alex Mykyta
2025-10-25 19:23:28 -07:00
parent d69af23be5
commit 1926aff7b1
3 changed files with 5 additions and 1 deletions
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2
src/peakrdl_regblock/field_logic/generators.py
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@@ -356,6 +356,7 @@ class FieldLogicGenerator(RDLForLoopGenerator):
bslice = "" bslice = ""
context = { context = {
'node': node,
"has_sw_writable": node.has_sw_writable, "has_sw_writable": node.has_sw_writable,
"has_sw_readable": node.has_sw_readable, "has_sw_readable": node.has_sw_readable,
"prefix": prefix, "prefix": prefix,
@@ -382,6 +383,7 @@ class FieldLogicGenerator(RDLForLoopGenerator):
retime = self.ds.retime_external_addrmap retime = self.ds.retime_external_addrmap
context = { context = {
'node': node,
"prefix": prefix, "prefix": prefix,
"strb": strb, "strb": strb,
"addr_width": addr_width, "addr_width": addr_width,

1
src/peakrdl_regblock/field_logic/templates/external_block.sv
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@@ -1,3 +1,4 @@
// External region: {{node.get_path()}}
{% if retime -%} {% if retime -%}

3
src/peakrdl_regblock/field_logic/templates/external_reg.sv
View File

@@ -1,3 +1,4 @@
// External register: {{node.get_path()}}
{% if retime -%} {% if retime -%}
@@ -29,7 +30,7 @@ end
{%- else -%} {%- else -%}
{%- if has_sw_readable and has_sw_writable %} {%- if has_sw_readable and has_sw_writable -%}
assign {{prefix}}.req = {{strb}}; assign {{prefix}}.req = {{strb}};
{%- elif has_sw_readable and not has_sw_writable %} {%- elif has_sw_readable and not has_sw_writable %}
assign {{prefix}}.req = !decoded_req_is_wr ? {{strb}} : '0; assign {{prefix}}.req = !decoded_req_is_wr ? {{strb}} : '0;