Add missing comment for external components

src/peakrdl_regblock/field_logic/generators.py

@@ -356,6 +356,7 @@ class FieldLogicGenerator(RDLForLoopGenerator):
             bslice = ""
 
         context = {
+            'node': node,
             "has_sw_writable": node.has_sw_writable,
             "has_sw_readable": node.has_sw_readable,
             "prefix": prefix,
@@ -382,6 +383,7 @@ class FieldLogicGenerator(RDLForLoopGenerator):
             retime = self.ds.retime_external_addrmap
 
         context = {
+            'node': node,
             "prefix": prefix,
             "strb": strb,
             "addr_width": addr_width,

src/peakrdl_regblock/field_logic/templates/external_block.sv

@@ -1,3 +1,4 @@
+// External region: {{node.get_path()}}
 {% if retime -%}
 
 

src/peakrdl_regblock/field_logic/templates/external_reg.sv

@@ -1,3 +1,4 @@
+// External register: {{node.get_path()}}
 {% if retime -%}
 
 
@@ -29,7 +30,7 @@ end
 {%- else -%}
 
 
-{%- if has_sw_readable and has_sw_writable %}
+{%- if has_sw_readable and has_sw_writable -%}
 assign {{prefix}}.req = {{strb}};
 {%- elif has_sw_readable and not has_sw_writable %}
 assign {{prefix}}.req = !decoded_req_is_wr ? {{strb}} : '0;