From 1aa9d8b603db6a87ec4af4c7ff00b94bf12bac03 Mon Sep 17 00:00:00 2001 From: Alex Mykyta Date: Tue, 27 Sep 2022 20:52:06 -0700 Subject: [PATCH] Move SV interface files into a common location. Add license info (#20) --- docs/cpuif/apb.rst | 4 +-- docs/cpuif/apb4.rst | 31 ------------------- docs/cpuif/axi4lite.rst | 2 +- docs/cpuif/customizing.rst | 2 +- hdl-src/README.md | 9 ++++++ .../lib/cpuifs/apb3 => hdl-src}/apb3_intf.sv | 0 .../lib/cpuifs/apb4 => hdl-src}/apb4_intf.sv | 0 .../axi4lite => hdl-src}/axi4lite_intf.sv | 0 tests/lib/cpuifs/apb3/__init__.py | 4 +-- tests/lib/cpuifs/apb4/__init__.py | 4 +-- tests/lib/cpuifs/axi4lite/__init__.py | 4 +-- 11 files changed, 19 insertions(+), 41 deletions(-) delete mode 100644 docs/cpuif/apb4.rst create mode 100644 hdl-src/README.md rename {tests/lib/cpuifs/apb3 => hdl-src}/apb3_intf.sv (100%) rename {tests/lib/cpuifs/apb4 => hdl-src}/apb4_intf.sv (100%) rename {tests/lib/cpuifs/axi4lite => hdl-src}/axi4lite_intf.sv (100%) diff --git a/docs/cpuif/apb.rst b/docs/cpuif/apb.rst index bd11b91..7cc149e 100644 --- a/docs/cpuif/apb.rst +++ b/docs/cpuif/apb.rst @@ -29,7 +29,7 @@ The APB3 CPU interface comes in two i/o port flavors: SystemVerilog Interface Class: :class:`peakrdl_regblock.cpuif.apb3.APB3_Cpuif` - Interface Definition: :download:`apb3_intf.sv <../../tests/lib/cpuifs/apb3/apb3_intf.sv>` + Interface Definition: :download:`apb3_intf.sv <../../hdl-src/apb3_intf.sv>` Flattened inputs/outputs Flattens the interface into discrete input and output ports. @@ -49,7 +49,7 @@ The APB4 CPU interface comes in two i/o port flavors: SystemVerilog Interface Class: :class:`peakrdl_regblock.cpuif.apb4.APB4_Cpuif` - Interface Definition: :download:`apb4_intf.sv <../../tests/lib/cpuifs/apb4/apb4_intf.sv>` + Interface Definition: :download:`apb4_intf.sv <../../hdl-src/apb4_intf.sv>` Flattened inputs/outputs Flattens the interface into discrete input and output ports. diff --git a/docs/cpuif/apb4.rst b/docs/cpuif/apb4.rst deleted file mode 100644 index 79d3c01..0000000 --- a/docs/cpuif/apb4.rst +++ /dev/null @@ -1,31 +0,0 @@ -AMBA 4 APB -========== - -Implements the register block using an -`AMBA 4 APB `_ -CPU interface. - -The APB4 CPU interface comes in two i/o port flavors: - -SystemVerilog Interface - Class: :class:`peakrdl_regblock.cpuif.apb4.APB4_Cpuif` - - Interface Definition: :download:`apb4_intf.sv <../../tests/lib/cpuifs/apb4/apb4_intf.sv>` - -Flattened inputs/outputs - Flattens the interface into discrete input and output ports. - - Class: :class:`peakrdl_regblock.cpuif.apb4.APB4_Cpuif_flattened` - - -.. warning:: - Some IP vendors will incorrectly implement the address signalling - assuming word-addresses. (that each increment of ``PADDR`` is the next word) - - For this exporter, values on the interface's ``PADDR`` input are interpreted - as byte-addresses. (a 32-bit APB bus increments ``PADDR`` in steps of 4) - Although APB protocol does not allow for unaligned transfers, this is in - accordance to the official AMBA bus specification. - - Be sure to double-check the interpretation of your interconnect IP. A simple - bit-shift operation can be used to correct this if necessary. diff --git a/docs/cpuif/axi4lite.rst b/docs/cpuif/axi4lite.rst index a70a656..7d0860d 100644 --- a/docs/cpuif/axi4lite.rst +++ b/docs/cpuif/axi4lite.rst @@ -12,7 +12,7 @@ The AXI4-Lite CPU interface comes in two i/o port flavors: SystemVerilog Interface Class: :class:`peakrdl_regblock.cpuif.axi4lite.AXI4Lite_Cpuif` - Interface Definition: :download:`axi4lite_intf.sv <../../tests/lib/cpuifs/axi4lite/axi4lite_intf.sv>` + Interface Definition: :download:`axi4lite_intf.sv <../../hdl-src/axi4lite_intf.sv>` Flattened inputs/outputs Flattens the interface into discrete input and output ports. diff --git a/docs/cpuif/customizing.rst b/docs/cpuif/customizing.rst index d77a616..8792534 100644 --- a/docs/cpuif/customizing.rst +++ b/docs/cpuif/customizing.rst @@ -13,7 +13,7 @@ to customize and existing CPUIF definition. As an example, let's use the SystemVerilog interface definition for :ref:`cpuif_axi4lite` that is bundled with this project. This interface uses - following style and naming conventions: +the following style and naming conventions: * SystemVerilog interface type name is ``axi4lite_intf`` * Defines modports named ``master`` and ``slave`` diff --git a/hdl-src/README.md b/hdl-src/README.md new file mode 100644 index 0000000..2136adb --- /dev/null +++ b/hdl-src/README.md @@ -0,0 +1,9 @@ +# HDL Source Files +This folder contains some SystemVerilog definitions that are useful collateral +to be used alongside this project. + +These reference files are free to use for any purpose and are not covered by +this project's GPLv3 license. + +If for whatever reason you feel the need to reference a license when using +these, then lets go with the [MIT License](https://choosealicense.com/licenses/mit/) diff --git a/tests/lib/cpuifs/apb3/apb3_intf.sv b/hdl-src/apb3_intf.sv similarity index 100% rename from tests/lib/cpuifs/apb3/apb3_intf.sv rename to hdl-src/apb3_intf.sv diff --git a/tests/lib/cpuifs/apb4/apb4_intf.sv b/hdl-src/apb4_intf.sv similarity index 100% rename from tests/lib/cpuifs/apb4/apb4_intf.sv rename to hdl-src/apb4_intf.sv diff --git a/tests/lib/cpuifs/axi4lite/axi4lite_intf.sv b/hdl-src/axi4lite_intf.sv similarity index 100% rename from tests/lib/cpuifs/axi4lite/axi4lite_intf.sv rename to hdl-src/axi4lite_intf.sv diff --git a/tests/lib/cpuifs/apb3/__init__.py b/tests/lib/cpuifs/apb3/__init__.py index 1cddce7..fffb098 100644 --- a/tests/lib/cpuifs/apb3/__init__.py +++ b/tests/lib/cpuifs/apb3/__init__.py @@ -5,10 +5,10 @@ from peakrdl_regblock.cpuif.apb3 import APB3_Cpuif, APB3_Cpuif_flattened class APB3(CpuifTestMode): cpuif_cls = APB3_Cpuif rtl_files = [ - "apb3_intf.sv", + "../../../../hdl-src/apb3_intf.sv", ] tb_files = [ - "apb3_intf.sv", + "../../../../hdl-src/apb3_intf.sv", "apb3_intf_driver.sv", ] tb_template = "tb_inst.sv" diff --git a/tests/lib/cpuifs/apb4/__init__.py b/tests/lib/cpuifs/apb4/__init__.py index 6ee31c9..4a93b67 100644 --- a/tests/lib/cpuifs/apb4/__init__.py +++ b/tests/lib/cpuifs/apb4/__init__.py @@ -5,10 +5,10 @@ from peakrdl_regblock.cpuif.apb4 import APB4_Cpuif, APB4_Cpuif_flattened class APB4(CpuifTestMode): cpuif_cls = APB4_Cpuif rtl_files = [ - "apb4_intf.sv", + "../../../../hdl-src/apb4_intf.sv", ] tb_files = [ - "apb4_intf.sv", + "../../../../hdl-src/apb4_intf.sv", "apb4_intf_driver.sv", ] tb_template = "tb_inst.sv" diff --git a/tests/lib/cpuifs/axi4lite/__init__.py b/tests/lib/cpuifs/axi4lite/__init__.py index 5249ff9..ef3147c 100644 --- a/tests/lib/cpuifs/axi4lite/__init__.py +++ b/tests/lib/cpuifs/axi4lite/__init__.py @@ -5,10 +5,10 @@ from peakrdl_regblock.cpuif.axi4lite import AXI4Lite_Cpuif, AXI4Lite_Cpuif_flatt class AXI4Lite(CpuifTestMode): cpuif_cls = AXI4Lite_Cpuif rtl_files = [ - "axi4lite_intf.sv", + "../../../../hdl-src/axi4lite_intf.sv", ] tb_files = [ - "axi4lite_intf.sv", + "../../../../hdl-src/axi4lite_intf.sv", "axi4lite_intf_driver.sv", ] tb_template = "tb_inst.sv"