Move SV interface files into a common location. Add license info (#20)

tests/lib/cpuifs/apb4/__init__.py

@@ -5,10 +5,10 @@ from peakrdl_regblock.cpuif.apb4 import APB4_Cpuif, APB4_Cpuif_flattened
 class APB4(CpuifTestMode):
     cpuif_cls = APB4_Cpuif
     rtl_files = [
-        "apb4_intf.sv",
+        "../../../../hdl-src/apb4_intf.sv",
     ]
     tb_files = [
-        "apb4_intf.sv",
+        "../../../../hdl-src/apb4_intf.sv",
         "apb4_intf_driver.sv",
     ]
     tb_template = "tb_inst.sv"

tests/lib/cpuifs/apb4/apb4_intf.sv

@@ -1,46 +0,0 @@
-interface apb4_intf #(
-    parameter DATA_WIDTH = 32,
-    parameter ADDR_WIDTH = 32
-);
-    // Command
-    logic PSEL;
-    logic PENABLE;
-    logic PWRITE;
-    logic [2:0] PPROT;
-    logic [ADDR_WIDTH-1:0] PADDR;
-    logic [DATA_WIDTH-1:0] PWDATA;
-    logic [DATA_WIDTH/8-1:0] PSTRB;
-
-    // Response
-    logic [DATA_WIDTH-1:0] PRDATA;
-    logic PREADY;
-    logic PSLVERR;
-
-    modport master (
-        output PSEL,
-        output PENABLE,
-        output PWRITE,
-        output PPROT,
-        output PADDR,
-        output PWDATA,
-        output PSTRB,
-
-        input PRDATA,
-        input PREADY,
-        input PSLVERR
-    );
-
-    modport slave (
-        input PSEL,
-        input PENABLE,
-        input PWRITE,
-        input PPROT,
-        input PADDR,
-        input PWDATA,
-        input PSTRB,
-
-        output PRDATA,
-        output PREADY,
-        output PSLVERR
-    );
-endinterface