bslathi19/PeakRDL-regblock
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Coverage improvements.

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This commit is contained in:
Alex Mykyta
2022-11-08 21:34:10 -08:00
parent fcfd5c09f4
commit 232faba417
4 changed files with 25 additions and 19 deletions
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4
docs/props/reg.rst
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@@ -6,9 +6,7 @@ Register Properties
accesswidth accesswidth
----------- -----------
|NO| |OK|
Only ``accesswidth`` that is equal to the ``regwidth`` is supported (default if unset)
regwidth regwidth
-------- --------

32
docs/props/rhs_props.rst
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@@ -20,7 +20,7 @@ Field
field -> swacc field -> swacc
^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^
|EX| |OK|
Single-cycle strobe that indicates the field is being accessed by software Single-cycle strobe that indicates the field is being accessed by software
(read or write). (read or write).
@@ -28,7 +28,7 @@ Single-cycle strobe that indicates the field is being accessed by software
field -> swmod field -> swmod
^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^
|EX| |OK|
Single-cycle strobe that indicates the field is being modified during a software Single-cycle strobe that indicates the field is being modified during a software
access operation. access operation.
@@ -43,7 +43,7 @@ Represents the signal that controls the field's swwe/swwel behavior.
field -> anded/ored/xored field -> anded/ored/xored
^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^
|EX| |OK|
Represents the current and/or/xor reduction of the field's value. Represents the current and/or/xor reduction of the field's value.
@@ -57,7 +57,7 @@ Represents the signal that controls the field's hwclr/hwset behavior.
field -> hwenable/hwmask field -> hwenable/hwmask
^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^
|EX| |OK|
Represents the signal that controls the field's hwenable/hwmask behavior. Represents the signal that controls the field's hwenable/hwmask behavior.
@@ -86,7 +86,7 @@ Field Counter Properties
field -> incr field -> incr
^^^^^^^^^^^^^ ^^^^^^^^^^^^^
|EX| |OK|
Represents the signal that controls the field's counter increment control. Represents the signal that controls the field's counter increment control.
@@ -121,7 +121,7 @@ exceeded its incrthreshold.
field -> incrvalue field -> incrvalue
^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^
|EX| |OK|
Represents the value that was assigned to this property. Represents the value that was assigned to this property.
@@ -133,7 +133,7 @@ Represents the event signal that is asserted when the counter is about to wrap.
field -> decr field -> decr
^^^^^^^^^^^^^ ^^^^^^^^^^^^^
|EX| |OK|
Represents the signal that controls the field's counter decrement control. Represents the signal that controls the field's counter decrement control.
@@ -167,7 +167,7 @@ exceeded its incrthreshold.
field -> decrvalue field -> decrvalue
^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^
|EX| |OK|
Represents the value that was assigned to this property. Represents the value that was assigned to this property.
@@ -184,19 +184,27 @@ Field Interrupt Properties
field -> enable field -> enable
^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^
|EX| |OK|
Represents the value that was assigned to this property.
field -> mask field -> mask
^^^^^^^^^^^^^ ^^^^^^^^^^^^^
|EX| |OK|
Represents the value that was assigned to this property.
field -> haltenable field -> haltenable
^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^
|EX| |OK|
Represents the value that was assigned to this property.
field -> haltmask field -> haltmask
^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^
|EX| |OK|
Represents the value that was assigned to this property.
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------

4
tests/test_counter_basics/regblock.rdl
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@@ -50,8 +50,8 @@ addrmap top {
updown2->decr = do_count_down; updown2->decr = do_count_down;
updown3->incr = do_count_up; updown3->incr = do_count_up;
updown3->decr = do_count_down; updown3->decr = do_count_down;
updown4->incr = do_count_up; updown4->incr = updown3->incr;
updown4->decr = do_count_down; updown4->decr = updown3->decr;
} simple @ 0x0; } simple @ 0x0;

4
tests/test_counter_saturate/regblock.rdl
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@@ -48,8 +48,8 @@ addrmap top {
count->decr = decrement; count->decr = decrement;
count->hwclr = clear; count->hwclr = clear;
count->hwset = set; count->hwset = set;
count->incrvalue = step;
count->decrvalue = step; count->decrvalue = step;
count->incrvalue = count->decrvalue;
} saturate_via_const @ 0x4; } saturate_via_const @ 0x4;
@@ -72,7 +72,7 @@ addrmap top {
count->hwclr = clear; count->hwclr = clear;
count->hwset = set; count->hwset = set;
count->incrvalue = step; count->incrvalue = step;
count->decrvalue = step; count->decrvalue = count->incrvalue;
} saturate_via_ref @ 0x8; } saturate_via_ref @ 0x8;
reg { reg {