bslathi19/PeakRDL-regblock
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First read/write!

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This commit is contained in:
Alex Mykyta
2021-11-16 23:29:58 -08:00
parent d5c5d42390
commit 249fc2df7c
33 changed files with 1332 additions and 202 deletions
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12
peakrdl/regblock/cpuif/apb4/__init__.py → peakrdl/regblock/cpuif/apb3/__init__.py
View File

@@ -1,17 +1,17 @@
from ..base import CpuifBase
class APB4_Cpuif(CpuifBase):
template_path = "cpuif/apb4/apb4_tmpl.sv"
class APB3_Cpuif(CpuifBase):
template_path = "cpuif/apb3/apb3_tmpl.sv"
@property
def port_declaration(self) -> str:
return "apb4_intf.slave s_apb"
return "apb3_intf.slave s_apb"
def signal(self, name:str) -> str:
return "s_apb." + name
return "s_apb." + name.upper()
class APB4_Cpuif_flattened(APB4_Cpuif):
class APB3_Cpuif_flattened(APB3_Cpuif):
@property
def port_declaration(self) -> str:
# TODO: Reference data/addr width from verilog parameter perhaps?
@@ -19,10 +19,8 @@ class APB4_Cpuif_flattened(APB4_Cpuif):
"input wire " + self.signal("psel"),
"input wire " + self.signal("penable"),
"input wire " + self.signal("pwrite"),
"input wire " + self.signal("pprot"),
f"input wire [{self.addr_width-1}:0] " + self.signal("paddr"),
f"input wire [{self.data_width-1}:0] " + self.signal("pwdata"),
f"input wire [{(self.data_width / 8)-1}:0] " + self.signal("pstrb"),
"output logic " + self.signal("pready"),
f"output logic [{self.data_width-1}:0] " + self.signal("prdata"),
"output logic " + self.signal("pslverr"),

5
peakrdl/regblock/cpuif/apb4/apb4_tmpl.sv → peakrdl/regblock/cpuif/apb3/apb3_tmpl.sv
View File

@@ -10,7 +10,6 @@ always_ff {{get_always_ff_event(cpuif_reset)}} begin
cpuif_req_is_wr <= '0;
cpuif_addr <= '0;
cpuif_wr_data <= '0;
cpuif_wr_bitstrb <= '0;
end else begin
if(~is_active) begin
if({{cpuif.signal("psel")}}) begin
@@ -19,9 +18,6 @@ always_ff {{get_always_ff_event(cpuif_reset)}} begin
cpuif_req_is_wr <= {{cpuif.signal("pwrite")}};
cpuif_addr <= {{cpuif.signal("paddr")}}[ADDR_WIDTH-1:0];
cpuif_wr_data <= {{cpuif.signal("pwdata")}};
for(int i=0; i<DATA_WIDTH/8; i++) begin
cpuif_wr_bitstrb[i*8 +: 8] <= {{"{8{"}}{{cpuif.signal("pstrb")}}[i]{{"}}"}};
end
end
end else begin
cpuif_req <= '0;
@@ -31,6 +27,7 @@ always_ff {{get_always_ff_event(cpuif_reset)}} begin
end
end
end
assign cpuif_wr_bitstrb = '0;
// Response
assign {{cpuif.signal("pready")}} = cpuif_rd_ack | cpuif_wr_ack;