First read/write!
This commit is contained in:
Alex Mykyta
372
test/test_regblock.sv
Normal file
372
test/test_regblock.sv
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// TODO: Add a banner
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module test_regblock (
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input wire clk,
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input wire rst,
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apb3_intf.slave s_apb,
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output test_regblock_pkg::test_regblock__out_t hwif_out
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);
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localparam ADDR_WIDTH = 32;
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localparam DATA_WIDTH = 32;
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//--------------------------------------------------------------------------
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// CPU Bus interface logic
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//--------------------------------------------------------------------------
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logic cpuif_req;
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logic cpuif_req_is_wr;
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logic [ADDR_WIDTH-1:0] cpuif_addr;
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logic [DATA_WIDTH-1:0] cpuif_wr_data;
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logic [DATA_WIDTH-1:0] cpuif_wr_bitstrb;
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logic cpuif_rd_ack;
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logic [DATA_WIDTH-1:0] cpuif_rd_data;
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logic cpuif_rd_err;
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logic cpuif_wr_ack;
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logic cpuif_wr_err;
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begin
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// Request
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logic is_active;
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always_ff @(posedge clk) begin
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if(rst) begin
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is_active <= '0;
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cpuif_req <= '0;
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cpuif_req_is_wr <= '0;
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cpuif_addr <= '0;
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cpuif_wr_data <= '0;
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end else begin
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if(~is_active) begin
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if(s_apb.PSEL) begin
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is_active <= '1;
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cpuif_req <= '1;
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cpuif_req_is_wr <= s_apb.PWRITE;
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cpuif_addr <= s_apb.PADDR[ADDR_WIDTH-1:0];
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cpuif_wr_data <= s_apb.PWDATA;
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end
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end else begin
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cpuif_req <= '0;
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if(cpuif_rd_ack || cpuif_wr_ack) begin
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is_active <= '0;
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end
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end
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end
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end
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assign cpuif_wr_bitstrb = '0;
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// Response
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assign s_apb.PREADY = cpuif_rd_ack | cpuif_wr_ack;
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assign s_apb.PRDATA = cpuif_rd_data;
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assign s_apb.PSLVERR = cpuif_rd_err | cpuif_wr_err;
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end
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//--------------------------------------------------------------------------
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// Address Decode
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//--------------------------------------------------------------------------
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typedef struct {
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logic r0;
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logic r1;
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logic r2;
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} decoded_reg_strb_t;
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decoded_reg_strb_t decoded_reg_strb;
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logic decoded_req;
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logic decoded_req_is_wr;
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logic [DATA_WIDTH-1:0] decoded_wr_data;
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logic [DATA_WIDTH-1:0] decoded_wr_bitstrb;
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always_comb begin
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decoded_reg_strb.r0 = cpuif_req & (cpuif_addr == 'h0);
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decoded_reg_strb.r1 = cpuif_req & (cpuif_addr == 'h100);
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decoded_reg_strb.r2 = cpuif_req & (cpuif_addr == 'h200);
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end
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// Writes are always granted with no error response
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assign cpuif_wr_ack = cpuif_req & cpuif_req_is_wr;
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assign cpuif_wr_err = '0;
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// Pass down signals to next stage
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assign decoded_req = cpuif_req;
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assign decoded_req_is_wr = cpuif_req_is_wr;
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assign decoded_wr_data = cpuif_wr_data;
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assign decoded_wr_bitstrb = cpuif_wr_bitstrb;
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//--------------------------------------------------------------------------
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// Field logic
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//--------------------------------------------------------------------------
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typedef struct {
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struct {
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struct {
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logic [7:0] next;
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logic load_next;
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} a;
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struct {
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logic [7:0] next;
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logic load_next;
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} b;
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struct {
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logic [7:0] next;
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logic load_next;
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} c;
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} r0;
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struct {
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struct {
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logic [7:0] next;
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logic load_next;
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} a;
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struct {
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logic [7:0] next;
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logic load_next;
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} b;
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struct {
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logic [7:0] next;
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logic load_next;
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} c;
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} r1;
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struct {
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struct {
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logic [7:0] next;
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logic load_next;
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} a;
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struct {
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logic [7:0] next;
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logic load_next;
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} b;
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struct {
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logic [7:0] next;
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logic load_next;
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} c;
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} r2;
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} field_combo_t;
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field_combo_t field_combo;
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typedef struct {
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struct {
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logic [7:0] a;
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logic [7:0] b;
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logic [7:0] c;
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} r0;
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struct {
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logic [7:0] a;
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logic [7:0] b;
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logic [7:0] c;
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} r1;
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struct {
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logic [7:0] a;
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logic [7:0] b;
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logic [7:0] c;
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} r2;
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} field_storage_t;
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field_storage_t field_storage;
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// Field: test_regblock.r0.a
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always_comb begin
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field_combo.r0.a.next = field_storage.r0.a;
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field_combo.r0.a.load_next = '0;
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if(decoded_reg_strb.r0 && decoded_req_is_wr) begin // SW write
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field_combo.r0.a.next = decoded_wr_data[7:0];
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field_combo.r0.a.load_next = '1;
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end
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end
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always_ff @(posedge clk) begin
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if(rst) begin
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field_storage.r0.a <= 'h10;
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end else if(field_combo.r0.a.load_next) begin
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field_storage.r0.a <= field_combo.r0.a.next;
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end
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end
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assign hwif_out.r0.a.value = field_storage.r0.a;
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assign hwif_out.r0.a.anded = &(field_storage.r0.a);
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// Field: test_regblock.r0.b
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always_comb begin
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field_combo.r0.b.next = field_storage.r0.b;
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field_combo.r0.b.load_next = '0;
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if(decoded_reg_strb.r0 && decoded_req_is_wr) begin // SW write
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field_combo.r0.b.next = decoded_wr_data[15:8];
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field_combo.r0.b.load_next = '1;
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end
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end
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always_ff @(posedge clk) begin
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if(rst) begin
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field_storage.r0.b <= 'h20;
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end else if(field_combo.r0.b.load_next) begin
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field_storage.r0.b <= field_combo.r0.b.next;
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end
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end
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assign hwif_out.r0.b.value = field_storage.r0.b;
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assign hwif_out.r0.b.ored = |(field_storage.r0.b);
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// Field: test_regblock.r0.c
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always_comb begin
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field_combo.r0.c.next = field_storage.r0.c;
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field_combo.r0.c.load_next = '0;
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if(decoded_reg_strb.r0 && decoded_req_is_wr) begin // SW write
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field_combo.r0.c.next = decoded_wr_data[23:16];
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field_combo.r0.c.load_next = '1;
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end
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end
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always_ff @(posedge clk) begin
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if(rst) begin
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field_storage.r0.c <= 'h30;
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end else if(field_combo.r0.c.load_next) begin
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field_storage.r0.c <= field_combo.r0.c.next;
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end
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end
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assign hwif_out.r0.c.value = field_storage.r0.c;
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assign hwif_out.r0.c.swmod = decoded_reg_strb.r0 && decoded_req_is_wr;
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// Field: test_regblock.r1.a
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always_comb begin
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field_combo.r1.a.next = field_storage.r1.a;
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field_combo.r1.a.load_next = '0;
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if(decoded_reg_strb.r1 && decoded_req_is_wr) begin // SW write
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field_combo.r1.a.next = decoded_wr_data[7:0];
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field_combo.r1.a.load_next = '1;
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end
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end
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always_ff @(posedge clk) begin
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if(rst) begin
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field_storage.r1.a <= 'h10;
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end else if(field_combo.r1.a.load_next) begin
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field_storage.r1.a <= field_combo.r1.a.next;
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end
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end
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assign hwif_out.r1.a.value = field_storage.r1.a;
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assign hwif_out.r1.a.anded = &(field_storage.r1.a);
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// Field: test_regblock.r1.b
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always_comb begin
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field_combo.r1.b.next = field_storage.r1.b;
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field_combo.r1.b.load_next = '0;
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if(decoded_reg_strb.r1 && decoded_req_is_wr) begin // SW write
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field_combo.r1.b.next = decoded_wr_data[15:8];
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field_combo.r1.b.load_next = '1;
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end
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end
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always_ff @(posedge clk) begin
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if(rst) begin
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field_storage.r1.b <= 'h20;
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end else if(field_combo.r1.b.load_next) begin
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field_storage.r1.b <= field_combo.r1.b.next;
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end
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end
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assign hwif_out.r1.b.value = field_storage.r1.b;
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assign hwif_out.r1.b.ored = |(field_storage.r1.b);
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// Field: test_regblock.r1.c
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always_comb begin
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field_combo.r1.c.next = field_storage.r1.c;
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field_combo.r1.c.load_next = '0;
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if(decoded_reg_strb.r1 && decoded_req_is_wr) begin // SW write
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field_combo.r1.c.next = decoded_wr_data[23:16];
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field_combo.r1.c.load_next = '1;
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end
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end
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always_ff @(posedge clk) begin
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if(rst) begin
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field_storage.r1.c <= 'h30;
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end else if(field_combo.r1.c.load_next) begin
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field_storage.r1.c <= field_combo.r1.c.next;
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end
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end
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assign hwif_out.r1.c.value = field_storage.r1.c;
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assign hwif_out.r1.c.swmod = decoded_reg_strb.r1 && decoded_req_is_wr;
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// Field: test_regblock.r2.a
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always_comb begin
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field_combo.r2.a.next = field_storage.r2.a;
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field_combo.r2.a.load_next = '0;
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if(decoded_reg_strb.r2 && decoded_req_is_wr) begin // SW write
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field_combo.r2.a.next = decoded_wr_data[7:0];
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field_combo.r2.a.load_next = '1;
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end
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end
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always_ff @(posedge clk) begin
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if(rst) begin
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field_storage.r2.a <= 'h10;
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end else if(field_combo.r2.a.load_next) begin
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field_storage.r2.a <= field_combo.r2.a.next;
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end
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end
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assign hwif_out.r2.a.value = field_storage.r2.a;
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assign hwif_out.r2.a.anded = &(field_storage.r2.a);
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// Field: test_regblock.r2.b
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always_comb begin
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field_combo.r2.b.next = field_storage.r2.b;
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field_combo.r2.b.load_next = '0;
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if(decoded_reg_strb.r2 && decoded_req_is_wr) begin // SW write
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field_combo.r2.b.next = decoded_wr_data[15:8];
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field_combo.r2.b.load_next = '1;
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end
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end
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always_ff @(posedge clk) begin
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if(rst) begin
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field_storage.r2.b <= 'h20;
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end else if(field_combo.r2.b.load_next) begin
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field_storage.r2.b <= field_combo.r2.b.next;
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end
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end
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assign hwif_out.r2.b.value = field_storage.r2.b;
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assign hwif_out.r2.b.ored = |(field_storage.r2.b);
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// Field: test_regblock.r2.c
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always_comb begin
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field_combo.r2.c.next = field_storage.r2.c;
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field_combo.r2.c.load_next = '0;
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if(decoded_reg_strb.r2 && decoded_req_is_wr) begin // SW write
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field_combo.r2.c.next = decoded_wr_data[23:16];
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field_combo.r2.c.load_next = '1;
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end
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end
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always_ff @(posedge clk) begin
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if(rst) begin
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field_storage.r2.c <= 'h30;
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end else if(field_combo.r2.c.load_next) begin
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field_storage.r2.c <= field_combo.r2.c.next;
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end
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end
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assign hwif_out.r2.c.value = field_storage.r2.c;
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assign hwif_out.r2.c.swmod = decoded_reg_strb.r2 && decoded_req_is_wr;
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//--------------------------------------------------------------------------
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// Readback
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//--------------------------------------------------------------------------
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logic readback_err;
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logic readback_done;
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logic [DATA_WIDTH-1:0] readback_data;
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logic [DATA_WIDTH-1:0] readback_array[3];
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assign readback_array[0][7:0] = (decoded_reg_strb.r0 && !decoded_req_is_wr) ? field_storage.r0.a : '0;
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assign readback_array[0][15:8] = (decoded_reg_strb.r0 && !decoded_req_is_wr) ? field_storage.r0.b : '0;
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assign readback_array[0][23:16] = (decoded_reg_strb.r0 && !decoded_req_is_wr) ? field_storage.r0.c : '0;
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assign readback_array[0][31:24] = '0;
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assign readback_array[1][7:0] = (decoded_reg_strb.r1 && !decoded_req_is_wr) ? field_storage.r1.a : '0;
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assign readback_array[1][15:8] = (decoded_reg_strb.r1 && !decoded_req_is_wr) ? field_storage.r1.b : '0;
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assign readback_array[1][23:16] = (decoded_reg_strb.r1 && !decoded_req_is_wr) ? field_storage.r1.c : '0;
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assign readback_array[1][31:24] = '0;
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assign readback_array[2][7:0] = (decoded_reg_strb.r2 && !decoded_req_is_wr) ? field_storage.r2.a : '0;
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assign readback_array[2][15:8] = (decoded_reg_strb.r2 && !decoded_req_is_wr) ? field_storage.r2.b : '0;
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assign readback_array[2][23:16] = (decoded_reg_strb.r2 && !decoded_req_is_wr) ? field_storage.r2.c : '0;
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assign readback_array[2][31:24] = '0;
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always_comb begin
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automatic logic [DATA_WIDTH-1:0] readback_data_var;
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readback_done = decoded_req & ~decoded_req_is_wr;
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readback_err = '0;
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readback_data_var = '0;
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for(int i=0; i<3; i++) begin
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readback_data_var |= readback_array[i];
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end
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readback_data = readback_data_var;
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end
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always_ff @(posedge clk) begin
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if(rst) begin
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cpuif_rd_ack <= '0;
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cpuif_rd_data <= '0;
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cpuif_rd_err <= '0;
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end else begin
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cpuif_rd_ack <= readback_done;
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cpuif_rd_data <= readback_data;
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cpuif_rd_err <= readback_err;
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end
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end
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endmodule
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