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Implement write buffering (#22)

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This commit is contained in:
Alex Mykyta
2022-10-24 21:49:47 -07:00
parent 808067fac9
commit 279a3c5788
29 changed files with 968 additions and 93 deletions
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1
src/peakrdl_regblock/addr_decode.py
View File

@@ -120,6 +120,7 @@ class DecodeLogicGenerator(RDLForLoopGenerator):
s = f"{self.addr_decode.get_access_strobe(node)} = cpuif_req_masked & (cpuif_addr == {self._get_address_str(node)});"
self.add_content(s)
else:
# Register is wide. Create a substrobe for each subword
n_subwords = regwidth // accesswidth
subword_stride = accesswidth // 8
for i in range(n_subwords):

12
src/peakrdl_regblock/exporter.py
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@@ -10,12 +10,13 @@ from .dereferencer import Dereferencer
from .readback import Readback
from .identifier_filter import kw_filter as kwf
from .cpuif import CpuifBase
from .cpuif.apb4 import APB4_Cpuif
from .hwif import Hwif
from .utils import get_always_ff_event
from .scan_design import DesignScanner
from .validate_design import DesignValidator
from .cpuif import CpuifBase
from .cpuif.apb4 import APB4_Cpuif
from .hwif import Hwif
from .write_buffering import WriteBuffering
class RegblockExporter:
def __init__(self, **kwargs: Any) -> None:
@@ -30,6 +31,7 @@ class RegblockExporter:
self.address_decode = AddressDecode(self)
self.field_logic = FieldLogic(self)
self.readback = None # type: Readback
self.write_buffering = None # type: WriteBuffering
self.dereferencer = Dereferencer(self)
self.min_read_latency = 0
self.min_write_latency = 0
@@ -143,6 +145,7 @@ class RegblockExporter:
self,
retime_read_fanin
)
self.write_buffering = WriteBuffering(self)
# Validate that there are no unsupported constructs
validator = DesignValidator(self)
@@ -153,8 +156,11 @@ class RegblockExporter:
"module_name": module_name,
"user_out_of_hier_signals": scanner.out_of_hier_signals.values(),
"has_writable_msb0_fields": scanner.has_writable_msb0_fields,
"has_buffered_write_regs": scanner.has_buffered_write_regs,
"has_buffered_read_regs": scanner.has_buffered_read_regs,
"cpuif": self.cpuif,
"hwif": self.hwif,
"write_buffering": self.write_buffering,
"get_resetsignal": self.dereferencer.get_resetsignal,
"address_decode": self.address_decode,
"field_logic": self.field_logic,

29
src/peakrdl_regblock/field_logic/__init__.py
View File

@@ -1,7 +1,6 @@
from typing import TYPE_CHECKING
from systemrdl.rdltypes import PropertyReference, PrecedenceType, InterruptType
from systemrdl.node import Node
from systemrdl.rdltypes import PrecedenceType, InterruptType
from .bases import AssignmentPrecedence, NextStateConditional
from . import sw_onread
@@ -186,19 +185,35 @@ class FieldLogic:
"""
w_modifiable = field.is_sw_writable
r_modifiable = (field.get_property('onread') is not None)
strb = self.exp.dereferencer.get_access_strobe(field)
buffer_writes = field.parent.get_property('buffer_writes')
if w_modifiable and not r_modifiable:
# assert swmod only on sw write
return f"{strb} && decoded_req_is_wr"
if buffer_writes:
# Write strobe arrives from buffer layer instead
wstrb = self.exp.write_buffering.get_write_strobe(field)
return wstrb
else:
# Unbuffered. Use decoder strobe directly
astrb = self.exp.dereferencer.get_access_strobe(field)
return f"{astrb} && decoded_req_is_wr"
if w_modifiable and r_modifiable:
# assert swmod on all sw actions
return strb
# assert swmod on both sw read and write
if buffer_writes:
astrb = self.exp.dereferencer.get_access_strobe(field)
wstrb = self.exp.write_buffering.get_write_strobe(field)
rstrb = f"{astrb} && !decoded_req_is_wr"
return f"{wstrb} || {rstrb}"
else:
# Unbuffered. Use decoder strobe directly
astrb = self.exp.dereferencer.get_access_strobe(field)
return astrb
if not w_modifiable and r_modifiable:
# assert swmod only on sw read
return f"{strb} && !decoded_req_is_wr"
astrb = self.exp.dereferencer.get_access_strobe(field)
return f"{astrb} && !decoded_req_is_wr"
# Not sw modifiable
return "1'b0"

2
src/peakrdl_regblock/field_logic/generators.py
View File

@@ -85,7 +85,7 @@ class FieldLogicGenerator(RDLForLoopGenerator):
super().__init__()
self.field_logic = field_logic
self.exp = field_logic.exp
self.field_storage_template = self.field_logic.exp.jj_env.get_template(
self.field_storage_template = self.exp.jj_env.get_template(
"field_logic/templates/field_storage.sv"
)
self.intr_fields = [] # type: List[FieldNode]

123
src/peakrdl_regblock/field_logic/sw_onwrite.py
View File

@@ -15,60 +15,104 @@ class _OnWrite(NextStateConditional):
return field.is_sw_writable and field.get_property('onwrite') == self.onwritetype
def get_predicate(self, field: 'FieldNode') -> str:
strb = self.exp.dereferencer.get_access_strobe(field)
if field.parent.get_property('buffer_writes'):
# Is buffered write. Use alternate strobe
wstrb = self.exp.write_buffering.get_write_strobe(field)
if field.get_property('swwe') or field.get_property('swwel'):
# dereferencer will wrap swwel complement if necessary
qualifier = self.exp.dereferencer.get_field_propref_value(field, 'swwe')
return f"{strb} && decoded_req_is_wr && {qualifier}"
if field.get_property('swwe') or field.get_property('swwel'):
# dereferencer will wrap swwel complement if necessary
qualifier = self.exp.dereferencer.get_field_propref_value(field, 'swwe')
return f"{wstrb} && {qualifier}"
return f"{strb} && decoded_req_is_wr"
return wstrb
else:
# is regular register
strb = self.exp.dereferencer.get_access_strobe(field)
def _wbus_bitslice(self, field: 'FieldNode', subword_idx: int) -> str:
if field.get_property('swwe') or field.get_property('swwel'):
# dereferencer will wrap swwel complement if necessary
qualifier = self.exp.dereferencer.get_field_propref_value(field, 'swwe')
return f"{strb} && decoded_req_is_wr && {qualifier}"
return f"{strb} && decoded_req_is_wr"
def _wbus_bitslice(self, field: 'FieldNode', subword_idx: int = 0) -> str:
# Get the source bitslice range from the internal cpuif's data bus
# For normal fields this ends up passing-through the field's low/high
# values unchanged.
# For fields within a wide register (accesswidth < regwidth), low/high
# may be shifted down and clamped depending on which sub-word is being accessed
accesswidth = field.parent.get_property('accesswidth')
if field.parent.get_property('buffer_writes'):
# register is buffered.
# write buffer is the full width of the register. no need to deal with subwords
high = field.high
low = field.low
if field.msb < field.lsb:
# slice is for an msb0 field.
# mirror it
regwidth = field.parent.get_property('regwidth')
low = regwidth - 1 - low
high = regwidth - 1 - high
low, high = high, low
else:
# Regular non-buffered register
# For normal fields this ends up passing-through the field's low/high
# values unchanged.
# For fields within a wide register (accesswidth < regwidth), low/high
# may be shifted down and clamped depending on which sub-word is being accessed
accesswidth = field.parent.get_property('accesswidth')
# Shift based on subword
high = field.high - (subword_idx * accesswidth)
low = field.low - (subword_idx * accesswidth)
# Shift based on subword
high = field.high - (subword_idx * accesswidth)
low = field.low - (subword_idx * accesswidth)
# clamp to accesswidth
high = max(min(high, accesswidth), 0)
low = max(min(low, accesswidth), 0)
# clamp to accesswidth
high = max(min(high, accesswidth), 0)
low = max(min(low, accesswidth), 0)
if field.msb < field.lsb:
# slice is for an msb0 field.
# mirror it
bus_width = self.exp.cpuif.data_width
low = bus_width - 1 - low
high = bus_width - 1 - high
low, high = high, low
if field.msb < field.lsb:
# slice is for an msb0 field.
# mirror it
bus_width = self.exp.cpuif.data_width
low = bus_width - 1 - low
high = bus_width - 1 - high
low, high = high, low
return f"[{high}:{low}]"
def _wr_data(self, field: 'FieldNode', subword_idx: int=0) -> str:
bslice = self._wbus_bitslice(field, subword_idx)
if field.msb < field.lsb:
# Field gets bitswapped since it is in [low:high] orientation
value = f"decoded_wr_data_bswap{bslice}"
if field.parent.get_property('buffer_writes'):
# Is buffered. Use value from write buffer
# No need to check msb0 ordering. Bus is pre-swapped, and bitslice
# accounts for it
bslice = self._wbus_bitslice(field)
wbuf_prefix = self.exp.write_buffering.get_wbuf_prefix(field)
return wbuf_prefix + ".data" + bslice
else:
value = f"decoded_wr_data{bslice}"
return value
# Regular non-buffered register
bslice = self._wbus_bitslice(field, subword_idx)
if field.msb < field.lsb:
# Field gets bitswapped since it is in [low:high] orientation
value = "decoded_wr_data_bswap" + bslice
else:
value = "decoded_wr_data" + bslice
return value
def _wr_biten(self, field: 'FieldNode', subword_idx: int=0) -> str:
bslice = self._wbus_bitslice(field, subword_idx)
if field.msb < field.lsb:
# Field gets bitswapped since it is in [low:high] orientation
value = f"decoded_wr_biten_bswap{bslice}"
if field.parent.get_property('buffer_writes'):
# Is buffered. Use value from write buffer
# No need to check msb0 ordering. Bus is pre-swapped, and bitslice
# accounts for it
bslice = self._wbus_bitslice(field)
wbuf_prefix = self.exp.write_buffering.get_wbuf_prefix(field)
return wbuf_prefix + ".biten" + bslice
else:
value = f"decoded_wr_biten{bslice}"
return value
# Regular non-buffered register
bslice = self._wbus_bitslice(field, subword_idx)
if field.msb < field.lsb:
# Field gets bitswapped since it is in [low:high] orientation
value = "decoded_wr_biten_bswap" + bslice
else:
value = "decoded_wr_biten" + bslice
return value
def get_assignments(self, field: 'FieldNode') -> List[str]:
accesswidth = field.parent.get_property("accesswidth")
@@ -92,6 +136,7 @@ class _OnWrite(NextStateConditional):
raise NotImplementedError
#-------------------------------------------------------------------------------
class WriteOneSet(_OnWrite):
comment = "SW write 1 set"
onwritetype = OnWriteType.woset

13
src/peakrdl_regblock/module_tmpl.sv
View File

@@ -108,6 +108,15 @@ module {{module_name}} (
assign cpuif_wr_ack = decoded_req & decoded_req_is_wr;
assign cpuif_wr_err = '0;
{%- if has_buffered_write_regs %}
//--------------------------------------------------------------------------
// Write double-buffers
//--------------------------------------------------------------------------
{{write_buffering.get_storage_struct()|indent}}
{{write_buffering.get_implementation()|indent}}
{%- endif %}
//--------------------------------------------------------------------------
// Field logic
//--------------------------------------------------------------------------
@@ -124,7 +133,6 @@ module {{module_name}} (
logic readback_done;
logic [{{cpuif.data_width-1}}:0] readback_data;
{{readback.get_implementation()|indent}}
{% if retime_read_response %}
always_ff {{get_always_ff_event(cpuif.reset)}} begin
if({{get_resetsignal(cpuif.reset)}}) begin
@@ -141,6 +149,5 @@ module {{module_name}} (
assign cpuif_rd_ack = readback_done;
assign cpuif_rd_data = readback_data;
assign cpuif_rd_err = readback_err;
{% endif %}
{%- endif %}
endmodule

5
src/peakrdl_regblock/readback/templates/readback.sv
View File

@@ -3,7 +3,9 @@
logic [{{cpuif.data_width-1}}:0] readback_array[{{array_size}}];
{{array_assignments}}
{% if do_fanin_stage %}
{%- if do_fanin_stage %}
// fanin stage
logic [{{cpuif.data_width-1}}:0] readback_array_c[{{fanin_array_size}}];
for(genvar g=0; g<{{fanin_loop_iter}}; g++) begin
@@ -48,6 +50,7 @@ always_comb begin
end
{%- else %}
// Reduce the array
always_comb begin
automatic logic [{{cpuif.data_width-1}}:0] readback_data_var;

30
src/peakrdl_regblock/scan_design.py
View File

@@ -26,6 +26,8 @@ class DesignScanner(RDLListener):
self.out_of_hier_signals = OrderedDict() # type: OrderedDict[str, SignalNode]
self.has_writable_msb0_fields = False
self.has_buffered_write_regs = False
self.has_buffered_read_regs = False
def _get_out_of_hier_field_reset(self) -> None:
current_node = self.exp.top_node.parent
@@ -69,19 +71,7 @@ class DesignScanner(RDLListener):
if node.external and (node != self.exp.top_node):
# Do not inspect external components. None of my business
return WalkerAction.SkipDescendants
return None
def enter_Reg(self, node: 'RegNode') -> None:
# The CPUIF's bus width is sized according to the largest accesswidth in the design
accesswidth = node.get_property('accesswidth')
self.cpuif_data_width = max(self.cpuif_data_width, accesswidth)
def enter_Signal(self, node: 'SignalNode') -> None:
if node.get_property('field_reset'):
path = node.get_path()
self.in_hier_signal_paths.add(path)
def enter_Field(self, node: 'FieldNode') -> None:
# Collect any signals that are referenced by a property
for prop_name in node.list_properties():
value = node.get_property(prop_name)
@@ -93,5 +83,21 @@ class DesignScanner(RDLListener):
else:
self.in_hier_signal_paths.add(path)
return None
def enter_Reg(self, node: 'RegNode') -> None:
# The CPUIF's bus width is sized according to the largest accesswidth in the design
accesswidth = node.get_property('accesswidth')
self.cpuif_data_width = max(self.cpuif_data_width, accesswidth)
self.has_buffered_write_regs = self.has_buffered_write_regs or node.get_property('buffer_writes')
self.has_buffered_read_regs = self.has_buffered_read_regs or node.get_property('buffer_reads')
def enter_Signal(self, node: 'SignalNode') -> None:
if node.get_property('field_reset'):
path = node.get_path()
self.in_hier_signal_paths.add(path)
def enter_Field(self, node: 'FieldNode') -> None:
if node.is_sw_writable and (node.msb < node.lsb):
self.has_writable_msb0_fields = True

23
src/peakrdl_regblock/udps.py
View File

@@ -3,7 +3,8 @@ from typing import Any
from systemrdl.udp import UDPDefinition
from systemrdl.component import Reg
from systemrdl.rdltypes.references import RefType, PropertyReference
from systemrdl.node import Node, RegNode, VectorNode
from systemrdl.rdltypes import NoValue
from systemrdl.node import Node, RegNode, VectorNode, SignalNode
class xBufferTrigger(UDPDefinition):
@@ -13,7 +14,12 @@ class xBufferTrigger(UDPDefinition):
def validate(self, node: Node, value: Any) -> None:
# TODO: Reference shall not cross an internal/external boundary
if isinstance(value, VectorNode):
if value is NoValue:
self.msg.error(
"Double-buffer trigger property is missing a value assignment",
self.get_src_ref(node)
)
elif isinstance(value, VectorNode):
# Trigger can reference a vector, but only if it is a single-bit
if value.width != 1:
self.msg.error(
@@ -24,6 +30,14 @@ class xBufferTrigger(UDPDefinition):
),
self.get_src_ref(node)
)
if isinstance(value, SignalNode):
if not value.get_property('activehigh') and not value.get_property('activelow'):
self.msg.error(
"Trigger was asigned a signal, but it does not specify whether it is activehigh/activelow",
self.get_src_ref(node)
)
elif isinstance(value, PropertyReference) and value.width is not None:
# Trigger can reference a property, but only if it is a single-bit
if value.width != 1:
@@ -54,7 +68,6 @@ class BufferWrites(UDPDefinition):
name = "buffer_writes"
valid_components = {Reg}
valid_type = bool
default_assignment = True
def validate(self, node: 'Node', value: Any) -> None:
assert isinstance(node, RegNode)
@@ -64,7 +77,6 @@ class BufferWrites(UDPDefinition):
"'buffer_writes' is set to true, but this register does not contain any writable fields.",
self.get_src_ref(node)
)
# TODO: Should I limit the use of other properties on double-buffered registers?
def get_unassigned_default(self, node: 'Node') -> Any:
return False
@@ -84,7 +96,6 @@ class BufferReads(UDPDefinition):
name = "buffer_reads"
valid_components = {Reg}
valid_type = bool
default_assignment = True
def validate(self, node: 'Node', value: Any) -> None:
assert isinstance(node, RegNode)
@@ -95,8 +106,6 @@ class BufferReads(UDPDefinition):
self.get_src_ref(node)
)
# TODO: Should I limit the use of other properties on double-buffered registers?
def get_unassigned_default(self, node: 'Node') -> Any:
return False

43
src/peakrdl_regblock/validate_design.py
View File

@@ -77,23 +77,30 @@ class DesignValidator(RDLListener):
def enter_Field(self, node: 'FieldNode') -> None:
# 10.6.1-f: Any field that is software-writable or clear on read shall
# not span multiple software accessible sub-words (e.g., a 64-bit
# register with a 32-bit access width may not have a writable field with
# bits in both the upper and lower half of the register).
#
# Interpreting this further - this rule applies any time a field is
# software-modifiable by any means, including rclr, rset, ruser
# TODO: suppress this check for registers that have the appropriate
# buffer_writes/buffer_reads UDP set
parent_accesswidth = node.parent.get_property('accesswidth')
parent_regwidth = node.parent.get_property('regwidth')
if ((parent_accesswidth < parent_regwidth)
and (node.lsb // parent_accesswidth) != (node.msb // parent_accesswidth)
and (node.is_sw_writable or node.get_property('onread') is not None)):
# Field spans across sub-words
self.msg.error(
f"Software-modifiable field '{node.inst_name}' shall not span "
"multiple software-accessible subwords.",
node.inst.inst_src_ref
)
if (
(parent_accesswidth < parent_regwidth)
and (node.lsb // parent_accesswidth) != (node.msb // parent_accesswidth)
):
# field spans multiple sub-words
if node.is_sw_writable and not node.parent.get_property('buffer_writes'):
# ... and is writable without the protection of double-buffering
# Enforce 10.6.1-f
self.msg.error(
f"Software-writable field '{node.inst_name}' shall not span"
" multiple software-accessible subwords. Consider enabling"
" write double-buffering.",
node.inst.inst_src_ref
)
if node.get_property('onread') is not None and not node.parent.get_property('buffer_reads'):
# ... is modified by an onread action without the atomicity of read buffering
# Enforce 10.6.1-f
self.msg.error(
f"The field '{node.inst_name}' spans multiple software-accessible"
" subwords and is modified on-read, making it impossible to"
" access its value correctly. Consider enabling read"
" double-buffering.",
node.inst.inst_src_ref
)

80
src/peakrdl_regblock/write_buffering/__init__.py Normal file
View File

@@ -0,0 +1,80 @@
from typing import TYPE_CHECKING, Union
from systemrdl.node import AddrmapNode, RegNode, FieldNode, SignalNode
from .storage_generator import WBufStorageStructGenerator
from .implementation_generator import WBufLogicGenerator
from ..utils import get_indexed_path
if TYPE_CHECKING:
from ..exporter import RegblockExporter
class WriteBuffering:
def __init__(self, exp:'RegblockExporter'):
self.exp = exp
@property
def top_node(self) -> 'AddrmapNode':
return self.exp.top_node
def get_storage_struct(self) -> str:
struct_gen = WBufStorageStructGenerator(self)
s = struct_gen.get_struct(self.top_node, "wbuf_storage_t")
assert s is not None
return s + "\nwbuf_storage_t wbuf_storage;"
def get_implementation(self) -> str:
gen = WBufLogicGenerator(self)
s = gen.get_content(self.top_node)
assert s is not None
return s
def get_wbuf_prefix(self, node: Union[RegNode, FieldNode]) -> str:
if isinstance(node, FieldNode):
node = node.parent
wbuf_prefix = "wbuf_storage." + get_indexed_path(self.top_node, node)
return wbuf_prefix
def get_write_strobe(self, node: Union[RegNode, FieldNode]) -> str:
prefix = self.get_wbuf_prefix(node)
return f"{prefix}.pending && {self.get_trigger(node)}"
def get_raw_trigger(self, node: 'RegNode') -> str:
trigger = node.get_property('wbuffer_trigger')
if isinstance(trigger, RegNode):
# Trigger is a register.
# trigger when uppermost address of the register is written
regwidth = node.get_property('regwidth')
accesswidth = node.get_property('accesswidth')
strb_prefix = self.exp.dereferencer.get_access_strobe(trigger, reduce_substrobes=False)
if accesswidth < regwidth:
n_subwords = regwidth // accesswidth
return f"{strb_prefix}[{n_subwords-1}] && decoded_req_is_wr"
else:
return f"{strb_prefix} && decoded_req_is_wr"
elif isinstance(trigger, SignalNode):
s = self.exp.dereferencer.get_value(trigger)
if trigger.get_property('activehigh'):
return s
else:
return f"~{s}"
else:
# Trigger is a field or propref bit
return self.exp.dereferencer.get_value(trigger)
def get_trigger(self, node: Union[RegNode, FieldNode]) -> str:
if isinstance(node, FieldNode):
node = node.parent
trigger = node.get_property('wbuffer_trigger')
if isinstance(trigger, RegNode) and trigger == node:
# register is its own trigger
# use the delayed trigger signal
return self.get_wbuf_prefix(node) + ".trigger_q"
else:
return self.get_raw_trigger(node)

60
src/peakrdl_regblock/write_buffering/implementation_generator.py Normal file
View File

@@ -0,0 +1,60 @@
from typing import TYPE_CHECKING
from collections import namedtuple
from systemrdl.component import Reg
from systemrdl.node import RegNode
from ..forloop_generator import RDLForLoopGenerator
from ..utils import get_always_ff_event
if TYPE_CHECKING:
from . import WriteBuffering
class WBufLogicGenerator(RDLForLoopGenerator):
i_type = "genvar"
def __init__(self, wbuf: 'WriteBuffering') -> None:
super().__init__()
self.wbuf = wbuf
self.exp = wbuf.exp
self.template = self.exp.jj_env.get_template(
"write_buffering/template.sv"
)
def enter_Reg(self, node: 'RegNode') -> None:
super().enter_Reg(node)
assert isinstance(node.inst, Reg)
if not node.get_property('buffer_writes'):
return
regwidth = node.get_property('regwidth')
accesswidth = node.get_property('accesswidth')
strb_prefix = self.exp.dereferencer.get_access_strobe(node, reduce_substrobes=False)
Segment = namedtuple("Segment", ["strobe", "bslice"])
segments = []
if accesswidth < regwidth:
n_subwords = regwidth // accesswidth
for i in range(n_subwords):
strobe = strb_prefix + f"[{i}]"
if node.inst.is_msb0_order:
bslice = f"[{regwidth - (accesswidth * i) - 1}: {regwidth - (accesswidth * (i+1))}]"
else:
bslice = f"[{(accesswidth * (i + 1)) - 1}:{accesswidth * i}]"
segments.append(Segment(strobe, bslice))
else:
segments.append(Segment(strb_prefix, ""))
trigger = node.get_property('wbuffer_trigger')
is_own_trigger = (isinstance(trigger, RegNode) and trigger == node)
context = {
'wbuf': self.wbuf,
'wbuf_prefix': self.wbuf.get_wbuf_prefix(node),
'segments': segments,
'node': node,
'cpuif': self.exp.cpuif,
'get_resetsignal': self.exp.dereferencer.get_resetsignal,
'get_always_ff_event': lambda resetsignal : get_always_ff_event(self.exp.dereferencer, resetsignal),
'is_own_trigger': is_own_trigger,
}
self.add_content(self.template.render(context))

32
src/peakrdl_regblock/write_buffering/storage_generator.py Normal file
View File

@@ -0,0 +1,32 @@
from typing import TYPE_CHECKING
from systemrdl.node import FieldNode, RegNode
from ..struct_generator import RDLStructGenerator
if TYPE_CHECKING:
from . import WriteBuffering
class WBufStorageStructGenerator(RDLStructGenerator):
def __init__(self, wbuf: 'WriteBuffering') -> None:
super().__init__()
self.wbuf = wbuf
def enter_Field(self, node: FieldNode) -> None:
# suppress parent class's field behavior
pass
def enter_Reg(self, node: RegNode) -> None:
super().enter_Reg(node)
if not node.get_property('buffer_writes'):
return
regwidth = node.get_property('regwidth')
self.add_member("data", regwidth)
self.add_member("biten", regwidth)
self.add_member("pending")
trigger = node.get_property('wbuffer_trigger')
if isinstance(trigger, RegNode) and trigger == node:
self.add_member("trigger_q")

31
src/peakrdl_regblock/write_buffering/template.sv Normal file
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@@ -0,0 +1,31 @@
always_ff {{get_always_ff_event(cpuif.reset)}} begin
if({{get_resetsignal(cpuif.reset)}}) begin
{{wbuf_prefix}}.pending <= '0;
{{wbuf_prefix}}.data <= '0;
{{wbuf_prefix}}.biten <= '0;
{%- if is_own_trigger %}
{{wbuf_prefix}}.trigger_q <= '0;
{%- endif %}
end else begin
{%- for segment in segments %}
if({{segment.strobe}} && decoded_req_is_wr) begin
{{wbuf_prefix}}.pending <= '1;
{%- if node.inst.is_msb0_order %}
{{wbuf_prefix}}.data{{segment.bslice}} <= decoded_wr_data_bswap;
{{wbuf_prefix}}.biten{{segment.bslice}} <= decoded_wr_biten_bswap;
{%- else %}
{{wbuf_prefix}}.data{{segment.bslice}} <= decoded_wr_data;
{{wbuf_prefix}}.biten{{segment.bslice}} <= decoded_wr_biten;
{%- endif %}
end
{%- endfor %}
{% if is_own_trigger %}
{{wbuf_prefix}}.trigger_q <= {{wbuf.get_raw_trigger(node)}};
{%- endif %}
if({{wbuf.get_trigger(node)}}) begin
{{wbuf_prefix}}.pending <= '0;
{{wbuf_prefix}}.data <= '0;
{{wbuf_prefix}}.biten <= '0;
end
end
end