From 280c3aad17ffe7b2623e51025f864aefaf2a5b11 Mon Sep 17 00:00:00 2001
From: Alex Mykyta <amykyta3@users.noreply.github.com>
Date: Thu, 24 Aug 2023 20:36:28 -0700
Subject: [PATCH] Discard LSbs of address for AXI4-Lite CPUIF to properly
 handle unaligned transfers. #60

---
 src/peakrdl_regblock/cpuif/apb3/apb3_tmpl.sv         |  2 +-
 src/peakrdl_regblock/cpuif/apb4/apb4_tmpl.sv         |  2 +-
 src/peakrdl_regblock/cpuif/axi4lite/axi4lite_tmpl.sv | 12 ++++++++++++
 3 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/src/peakrdl_regblock/cpuif/apb3/apb3_tmpl.sv b/src/peakrdl_regblock/cpuif/apb3/apb3_tmpl.sv
index e51198d..bcd45ea 100644
--- a/src/peakrdl_regblock/cpuif/apb3/apb3_tmpl.sv
+++ b/src/peakrdl_regblock/cpuif/apb3/apb3_tmpl.sv
@@ -13,7 +13,7 @@ always_ff {{get_always_ff_event(cpuif.reset)}} begin
                 is_active <= '1;
                 cpuif_req <= '1;
                 cpuif_req_is_wr <= {{cpuif.signal("pwrite")}};
-                {%- if cpuif.data_width == 8 %}
+                {%- if cpuif.data_width_bytes == 1 %}
                 cpuif_addr <= {{cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:0];
                 {%- else %}
                 cpuif_addr <= { {{-cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
diff --git a/src/peakrdl_regblock/cpuif/apb4/apb4_tmpl.sv b/src/peakrdl_regblock/cpuif/apb4/apb4_tmpl.sv
index bdc5c44..34f51b6 100644
--- a/src/peakrdl_regblock/cpuif/apb4/apb4_tmpl.sv
+++ b/src/peakrdl_regblock/cpuif/apb4/apb4_tmpl.sv
@@ -14,7 +14,7 @@ always_ff {{get_always_ff_event(cpuif.reset)}} begin
                 is_active <= '1;
                 cpuif_req <= '1;
                 cpuif_req_is_wr <= {{cpuif.signal("pwrite")}};
-                {%- if cpuif.data_width == 8 %}
+                {%- if cpuif.data_width_bytes == 1 %}
                 cpuif_addr <= {{cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:0];
                 {%- else %}
                 cpuif_addr <= { {{-cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
diff --git a/src/peakrdl_regblock/cpuif/axi4lite/axi4lite_tmpl.sv b/src/peakrdl_regblock/cpuif/axi4lite/axi4lite_tmpl.sv
index 5e4734e..5b68c19 100644
--- a/src/peakrdl_regblock/cpuif/axi4lite/axi4lite_tmpl.sv
+++ b/src/peakrdl_regblock/cpuif/axi4lite/axi4lite_tmpl.sv
@@ -83,17 +83,29 @@ always_comb begin
         if(axil_arvalid && !axil_prev_was_rd) begin
             cpuif_req = '1;
             cpuif_req_is_wr = '0;
+            {%- if cpuif.data_width_bytes == 1 %}
             cpuif_addr = axil_araddr;
+            {%- else %}
+            cpuif_addr = {axil_araddr[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
+            {%- endif %}
             if(!cpuif_req_stall_rd) axil_ar_accept = '1;
         end else if(axil_awvalid && axil_wvalid) begin
             cpuif_req = '1;
             cpuif_req_is_wr = '1;
+            {%- if cpuif.data_width_bytes == 1 %}
             cpuif_addr = axil_awaddr;
+            {%- else %}
+            cpuif_addr = {axil_awaddr[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
+            {%- endif %}
             if(!cpuif_req_stall_wr) axil_aw_accept = '1;
         end else if(axil_arvalid) begin
             cpuif_req = '1;
             cpuif_req_is_wr = '0;
+            {%- if cpuif.data_width_bytes == 1 %}
             cpuif_addr = axil_araddr;
+            {%- else %}
+            cpuif_addr = {axil_araddr[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
+            {%- endif %}
             if(!cpuif_req_stall_rd) axil_ar_accept = '1;
         end
     end