From 2e37e580f6278dc58fa5ea177665f1094e39568d Mon Sep 17 00:00:00 2001 From: Alex Mykyta Date: Fri, 21 Apr 2023 21:50:33 -0700 Subject: [PATCH] simplify cpuif base cls --- src/peakrdl_regblock/cpuif/base.py | 7 +++---- src/peakrdl_regblock/exporter.py | 1 - 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/src/peakrdl_regblock/cpuif/base.py b/src/peakrdl_regblock/cpuif/base.py index 2d63a86..778ebdc 100644 --- a/src/peakrdl_regblock/cpuif/base.py +++ b/src/peakrdl_regblock/cpuif/base.py @@ -1,4 +1,4 @@ -from typing import TYPE_CHECKING, Optional +from typing import TYPE_CHECKING import inspect import os @@ -8,16 +8,15 @@ from ..utils import get_always_ff_event, clog2, is_pow2, roundup_pow2 if TYPE_CHECKING: from ..exporter import RegblockExporter - from systemrdl import SignalNode class CpuifBase: # Path is relative to the location of the class that assigns this variable template_path = "" - def __init__(self, exp:'RegblockExporter', cpuif_reset:Optional['SignalNode'], data_width:int=32, addr_width:int=32): + def __init__(self, exp:'RegblockExporter', data_width:int=32, addr_width:int=32): self.exp = exp - self.reset = cpuif_reset + self.reset = exp.top_node.cpuif_reset self.data_width = data_width self.addr_width = addr_width diff --git a/src/peakrdl_regblock/exporter.py b/src/peakrdl_regblock/exporter.py index 9cc364f..8f0dafa 100644 --- a/src/peakrdl_regblock/exporter.py +++ b/src/peakrdl_regblock/exporter.py @@ -153,7 +153,6 @@ class RegblockExporter: # Construct exporter components self.cpuif = cpuif_cls( self, - cpuif_reset=self.top_node.cpuif_reset, data_width=scanner.cpuif_data_width, addr_width=addr_width )