Add passthrough CPUIF

peakrdl/regblock/cpuif/apb3/apb3_tmpl.sv

@@ -1,6 +1,3 @@
-{% extends "cpuif/base_tmpl.sv" %}
-
-{% block body %}
 // Request
 logic is_active;
 always_ff {{get_always_ff_event(cpuif.reset)}} begin
@@ -36,4 +33,3 @@ end
 assign {{cpuif.signal("pready")}} = cpuif_rd_ack | cpuif_wr_ack;
 assign {{cpuif.signal("prdata")}} = cpuif_rd_data;
 assign {{cpuif.signal("pslverr")}} = cpuif_rd_err | cpuif_wr_err;
-{%- endblock body%}

peakrdl/regblock/cpuif/base.py

@@ -7,7 +7,7 @@ if TYPE_CHECKING:
     from systemrdl import SignalNode
 
 class CpuifBase:
-    template_path = "cpuif/base_tmpl.sv"
+    template_path = ""
 
     def __init__(self, exp:'RegblockExporter', cpuif_reset:Optional['SignalNode'], data_width:int=32, addr_width:int=32):
         self.exp = exp

peakrdl/regblock/cpuif/base_tmpl.sv

@@ -1,2 +0,0 @@
-{%- block body %}
-{%- endblock %}

peakrdl/regblock/cpuif/passthrough/__init__.py

@@ -0,0 +1,19 @@
+from ..base import CpuifBase
+
+class PassthroughCpuif(CpuifBase):
+    template_path = "cpuif/passthrough/passthrough_tmpl.sv"
+
+    @property
+    def port_declaration(self) -> str:
+        lines = [
+            "input wire s_cpuif_req",
+            "input wire s_cpuif_req_is_wr",
+            f"input wire [{self.addr_width-1}:0] s_cpuif_addr",
+            f"input wire [{self.data_width-1}:0] s_cpuif_wr_data",
+            "output wire s_cpuif_rd_ack",
+            "output wire s_cpuif_rd_err",
+            f"output wire [{self.data_width-1}:0] s_cpuif_rd_data",
+            "output wire s_cpuif_wr_ack",
+            "output wire s_cpuif_wr_err",
+        ]
+        return ",\n".join(lines)

peakrdl/regblock/cpuif/passthrough/passthrough_tmpl.sv

@@ -0,0 +1,9 @@
+assign cpuif_req = s_cpuif_req;
+assign cpuif_req_is_wr = s_cpuif_req_is_wr;
+assign cpuif_addr = s_cpuif_addr;
+assign cpuif_wr_data = s_cpuif_wr_data;
+assign s_cpuif_rd_ack = cpuif_rd_ack;
+assign s_cpuif_rd_err = cpuif_rd_err;
+assign s_cpuif_rd_data = cpuif_rd_data;
+assign s_cpuif_wr_ack = cpuif_wr_ack;
+assign s_cpuif_wr_err = cpuif_wr_err;

peakrdl/regblock/exporter.py

@@ -106,7 +106,6 @@ class RegblockExporter:
         context = {
             "module_name": module_name,
             "user_out_of_hier_signals": scanner.out_of_hier_signals.values(),
-            "interrupts": [], # TODO:
             "cpuif": self.cpuif,
             "hwif": self.hwif,
             "get_resetsignal": self.dereferencer.get_resetsignal,

peakrdl/regblock/module_tmpl.sv

@@ -11,10 +11,6 @@ module {{module_name}} (
         {%- endif %}
         {%- endfor %}
 
-        {%- for interrupt in interrupts %}
-        // TODO:
-        {%- endfor %}
-
         {{cpuif.port_declaration|indent(8)}}
         {%- if hwif.has_input_struct or hwif.has_output_struct %},{% endif %}
 
@@ -30,8 +26,8 @@ module {{module_name}} (
     logic [{{cpuif.data_width-1}}:0] cpuif_wr_data;
 
     logic cpuif_rd_ack;
-    logic [{{cpuif.data_width-1}}:0] cpuif_rd_data;
     logic cpuif_rd_err;
+    logic [{{cpuif.data_width-1}}:0] cpuif_rd_data;
 
     logic cpuif_wr_ack;
     logic cpuif_wr_err;