diff --git a/docs/api.rst b/docs/api.rst
index b949c0f..69b809d 100644
--- a/docs/api.rst
+++ b/docs/api.rst
@@ -2,7 +2,7 @@ Exporter API
 ============
 
 If you are not using the `PeakRDL command-line tool <https://peakrdl.readthedocs.io>`_,
-you can still generate regblocks programmaticaly using the exporter API:
+you can still generate regblocks programmatically using the exporter API:
 
 .. autoclass:: peakrdl_regblock.RegblockExporter
     :members:
diff --git a/docs/configuring.rst b/docs/configuring.rst
index 425ecee..6be6f63 100644
--- a/docs/configuring.rst
+++ b/docs/configuring.rst
@@ -5,7 +5,7 @@ Configuring PeakRDL-regblock
 
 If using the `PeakRDL command line tool <https://peakrdl.readthedocs.io/>`_,
 some aspects of the ``regblock`` command have additional configuration options
-avaiable via the PeakRDL TOML file.
+available via the PeakRDL TOML file.
 
 All regblock-specific options are defined under the ``[regblock]`` TOML heading.
 
diff --git a/docs/cpuif/customizing.rst b/docs/cpuif/customizing.rst
index 4f888f5..a354cbc 100644
--- a/docs/cpuif/customizing.rst
+++ b/docs/cpuif/customizing.rst
@@ -92,33 +92,22 @@ The easiest way to add your cpuif is via the TOML config file. See the
 
 Via a package's entry point definition
 --------------------------------------
-If you are publishing a collecxtion of PeakRDL plugins as an installable Python
+If you are publishing a collection of PeakRDL plugins as an installable Python
 package, you can advertise them to PeakRDL using an entry point.
 This advertises your custom CPUIF class to the PeakRDL-regblock tool as a plugin
 that should be loaded, and made available as a command-line option in PeakRDL.
 
-.. code-block:: python
-    :emphasize-lines: 7-11
+.. code-block:: toml
 
-    import setuptools
-
-    setuptools.setup(
-        name="my_package",
-        packages=["my_package"],
-        # ...
-        entry_points = {
-            "peakrdl_regblock.cpuif": [
-                'my-cpuif = my_package.__peakrdl_regblock__:MyCPUIF'
-            ]
-        }
-    )
+    [project.entry-points."peakrdl_regblock.cpuif"]
+    my-cpuif = "my_package.my_module:MyCPUIF"
 
 
 *   ``my_package``: The name of your installable Python module
 *   ``peakrdl-regblock.cpuif``: This is the namespace that PeakRDL-regblock will
     search. Any cpuif plugins you create must be enclosed in this namespace in
     order to be discovered.
-*   ``my_package.__peakrdl_regblock__:MyCPUIF``: This is the import path that
+*   ``my_package.my_module:MyCPUIF``: This is the import path that
     points to your CPUIF class definition.
 *   ``my-cpuif``: The lefthand side of the assignment is your cpuif's name. This
     text is what the end-user uses in the command line interface to select your
diff --git a/docs/cpuif/introduction.rst b/docs/cpuif/introduction.rst
index 47f55ff..126bc0e 100644
--- a/docs/cpuif/introduction.rst
+++ b/docs/cpuif/introduction.rst
@@ -11,7 +11,7 @@ Bus Width
 ^^^^^^^^^
 The CPU interface bus width is automatically determined from the contents of the
 design being exported. The bus width is equal to the widest ``accesswidth``
-encountered in the deisgn.
+encountered in the design.
 
 
 Addressing
diff --git a/docs/udps/read_buffering.rst b/docs/udps/read_buffering.rst
index 3f61b89..41a175e 100644
--- a/docs/udps/read_buffering.rst
+++ b/docs/udps/read_buffering.rst
@@ -108,7 +108,7 @@ Atomic Group of Registers
 ^^^^^^^^^^^^^^^^^^^^^^^^^
 Perhaps you have a group of registers that monitor some rapidly-changing state
 within your design. Using the ``rbuffer_trigger`` property, you can define which
-reagister read operation triggers the buffered registers' values to be latched.
+register read operation triggers the buffered registers' values to be latched.
 
 .. code-block:: systemrdl
     :emphasize-lines: 11-14
diff --git a/src/peakrdl_regblock/utils.py b/src/peakrdl_regblock/utils.py
index 1074f89..1de18d4 100644
--- a/src/peakrdl_regblock/utils.py
+++ b/src/peakrdl_regblock/utils.py
@@ -49,6 +49,8 @@ def ref_is_internal(top_node: AddrmapNode, ref: Union[Node, PropertyReference])
         current_node = ref
     elif isinstance(ref, PropertyReference):
         current_node = ref.node
+    else:
+        raise RuntimeError
 
     while current_node is not None:
         if current_node == top_node:
@@ -63,7 +65,7 @@ def ref_is_internal(top_node: AddrmapNode, ref: Union[Node, PropertyReference])
         current_node = current_node.parent
 
     # A root signal was referenced, which dodged the top addrmap
-    # This is considerd internal for this exporter
+    # This is considered internal for this exporter
     return True
 
 
diff --git a/tests/README.md b/tests/README.md
index 528d0b7..bb3996c 100644
--- a/tests/README.md
+++ b/tests/README.md
@@ -9,7 +9,7 @@ commands to be visible via the PATH environment variable.
 *Questa - Intel FPGA Starter Edition* can be downloaded for free from Intel:
 * Go to https://www.intel.com/content/www/us/en/collections/products/fpga/software/downloads.html?edition=pro&q=questa&s=Relevancy
 * Select latest version of Questa
-* Download Questa files. (Don't forget part 2!)
+* Download Questa files.
 * Install
     * Be sure to choose "Starter Edition" for the free version.
 * Create an account on https://licensing.intel.com