bslathi19/PeakRDL-regblock
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Alex Mykyta
2021-12-04 17:24:19 -08:00
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[![Documentation Status](https://readthedocs.org/projects/peakrdl-regblock/badge/?version=latest)](http://peakrdl-regblock.readthedocs.io)
[![PyPI - Python Version](https://img.shields.io/pypi/pyversions/peakrdl-regblock.svg)](https://pypi.org/project/peakrdl-regblock)
# IMPORTANT
This project has no official releases yet and is still under active development!
# PeakRDL-regblock
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
## Installing
(Not published to PyPi yet)
## Documentation
See the [PeakRDL-regblock Documentation](http://peakrdl-regblock.readthedocs.io) for more details