More testcases & documentation

test/lib/cpuifs/apb3/tb_inst.sv

@@ -1,3 +1,4 @@
+{% sv_line_anchor %}
 apb3_intf #(
     .DATA_WIDTH({{exporter.cpuif.data_width}}),
     .ADDR_WIDTH({{exporter.cpuif.addr_width}})
@@ -11,6 +12,7 @@ apb3_intf_driver #(
     .m_apb(s_apb)
 );
 {% if type(cpuif).__name__.startswith("Flat") %}
+{% sv_line_anchor %}
 wire s_apb_psel;
 wire s_apb_penable;
 wire s_apb_pwrite;

test/lib/cpuifs/base.py

@@ -6,6 +6,8 @@ import jinja2 as jj
 
 from peakrdl.regblock.cpuif.base import CpuifBase
 
+from ..sv_line_anchor import SVLineAnchor
+
 if TYPE_CHECKING:
     from peakrdl.regblock import RegblockExporter
     from ..regblock_testcase import RegblockTestCase
@@ -30,13 +32,17 @@ class CpuifTestMode:
 
 
     def get_tb_inst(self, tb_cls: 'RegblockTestCase', exporter: 'RegblockExporter') -> str:
-        class_dir = os.path.dirname(inspect.getfile(self.__class__))
+
+        # For consistency, make the template root path relative to the test dir
+        template_root_path = os.path.join(os.path.dirname(__file__), "../..")
+
         loader = jj.FileSystemLoader(
-            os.path.join(class_dir)
+            template_root_path
         )
         jj_env = jj.Environment(
             loader=loader,
             undefined=jj.StrictUndefined,
+            extensions=[SVLineAnchor],
         )
 
         context = {
@@ -46,5 +52,11 @@ class CpuifTestMode:
             "type": type,
         }
 
-        template = jj_env.get_template(self.tb_template)
+        # template paths are relative to their class.
+        # transform to be relative to the root path
+        class_dir = os.path.dirname(inspect.getfile(self.__class__))
+        template_local_path = os.path.join(class_dir, self.tb_template)
+        template_path = os.path.relpath(template_local_path, template_root_path)
+        template = jj_env.get_template(template_path)
+
         return template.render(context)

test/lib/regblock_testcase.py

@@ -5,11 +5,14 @@ import glob
 import shutil
 import subprocess
 import inspect
+import pathlib
 
 import pytest
 import jinja2 as jj
 from systemrdl import RDLCompiler
 
+from .sv_line_anchor import SVLineAnchor
+
 from peakrdl.regblock import RegblockExporter
 from .cpuifs.base import CpuifTestMode
 from .cpuifs.apb3 import APB3
@@ -53,7 +56,7 @@ class RegblockTestCase(unittest.TestCase):
     @classmethod
     def get_build_dir(cls) -> str:
         this_dir = cls.get_testcase_dir()
-        build_dir = os.path.join(this_dir, cls.__name__ + ".out")
+        build_dir = os.path.join(this_dir, "run.out", cls.__name__)
         return build_dir
 
     @classmethod
@@ -113,6 +116,7 @@ class RegblockTestCase(unittest.TestCase):
         jj_env = jj.Environment(
             loader=loader,
             undefined=jj.StrictUndefined,
+            extensions=[SVLineAnchor],
         )
 
         context = {
@@ -121,7 +125,7 @@ class RegblockTestCase(unittest.TestCase):
         }
 
         # template path needs to be relative to the Jinja loader root
-        template_path = os.path.join(cls.get_testcase_dir(), "tb.sv")
+        template_path = os.path.join(cls.get_testcase_dir(), "tb_template.sv")
         template_path = os.path.relpath(template_path, template_root_path)
         template = jj_env.get_template(template_path)
 
@@ -173,7 +177,7 @@ class RegblockTestCase(unittest.TestCase):
         build_dir = cls.get_build_dir()
         if os.path.exists(build_dir):
             shutil.rmtree(build_dir)
-        os.mkdir(build_dir)
+        pathlib.Path(build_dir).mkdir(parents=True, exist_ok=True)
 
         cls._write_params()
 

test/lib/sv_line_anchor.py

@@ -0,0 +1,10 @@
+from jinja2_simple_tags import StandaloneTag
+
+class SVLineAnchor(StandaloneTag):
+    """
+    Define a custom Jinja tag that emits a SystemVerilog `line directive so that
+    assertion messages can get properly back-annotated
+    """
+    tags = {"sv_line_anchor"}
+    def render(self):
+        return f'`line {self.lineno + 1} "{self.template}" 0'

test/lib/templates/tb_base.sv

@@ -1,3 +1,4 @@
+{% sv_line_anchor %}
 module tb;
     timeunit 1ns;
     timeprecision 1ps;
@@ -51,9 +52,11 @@ module tb;
     //--------------------------------------------------------------------------
     // DUT
     //--------------------------------------------------------------------------
+    {% sv_line_anchor %}
     regblock dut (.*);
 
 {%- if exporter.hwif.has_output_struct %}
+    {% sv_line_anchor %}
     initial forever begin
         ##1; if(!rst) assert(!$isunknown({>>{hwif_out}})) else $error("hwif_out has X's!");
     end
@@ -82,6 +85,7 @@ module tb;
     //--------------------------------------------------------------------------
     // Monitor for timeout
     //--------------------------------------------------------------------------
+    {% sv_line_anchor %}
     initial begin
         ##{{cls.timeout_clk_cycles}};
         $fatal(1, "Test timed out after {{cls.timeout_clk_cycles}} clock cycles");