bslathi19/PeakRDL-regblock
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

More testcases & documentation

Browse Source
This commit is contained in:
Alex Mykyta
2021-12-04 17:24:19 -08:00
parent f70bdf774c
commit 3adf7e1328
44 changed files with 827 additions and 63 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
test/lib/templates/tb_base.sv
View File

@@ -1,3 +1,4 @@
{% sv_line_anchor %}
module tb;
timeunit 1ns;
timeprecision 1ps;
@@ -51,9 +52,11 @@ module tb;
//--------------------------------------------------------------------------
// DUT
//--------------------------------------------------------------------------
{% sv_line_anchor %}
regblock dut (.*);
{%- if exporter.hwif.has_output_struct %}
{% sv_line_anchor %}
initial forever begin
##1; if(!rst) assert(!$isunknown({>>{hwif_out}})) else $error("hwif_out has X's!");
end
@@ -82,6 +85,7 @@ module tb;
//--------------------------------------------------------------------------
// Monitor for timeout
//--------------------------------------------------------------------------
{% sv_line_anchor %}
initial begin
##{{cls.timeout_clk_cycles}};
$fatal(1, "Test timed out after {{cls.timeout_clk_cycles}} clock cycles");