Add APB4 cpuif

src/peakrdl_regblock/__peakrdl__.py

@@ -1,7 +1,7 @@
 from typing import TYPE_CHECKING
 
 from .exporter import RegblockExporter
-from .cpuif import apb3, axi4lite, passthrough
+from .cpuif import apb3, apb4, axi4lite, passthrough
 
 if TYPE_CHECKING:
     import argparse
@@ -12,6 +12,8 @@ if TYPE_CHECKING:
 CPUIF_DICT = {
     "apb3": apb3.APB3_Cpuif,
     "apb3-flat": apb3.APB3_Cpuif_flattened,
+    "apb4": apb4.APB4_Cpuif,
+    "apb4-flat": apb4.APB4_Cpuif_flattened,
     "axi4-lite": axi4lite.AXI4Lite_Cpuif,
     "axi4-lite-flat": axi4lite.AXI4Lite_Cpuif_flattened,
     "passthrough": passthrough.PassthroughCpuif

src/peakrdl_regblock/cpuif/apb4/__init__.py

@@ -0,0 +1,36 @@
+from ..base import CpuifBase
+
+class APB4_Cpuif(CpuifBase):
+    template_path = "apb4_tmpl.sv"
+
+    @property
+    def port_declaration(self) -> str:
+        return "apb4_intf.slave s_apb"
+
+    def signal(self, name:str) -> str:
+        return "s_apb." + name.upper()
+
+    @property
+    def data_width_bytes(self) -> int:
+        return self.data_width // 8
+
+
+class APB4_Cpuif_flattened(APB4_Cpuif):
+    @property
+    def port_declaration(self) -> str:
+        lines = [
+            "input wire " + self.signal("psel"),
+            "input wire " + self.signal("penable"),
+            "input wire " + self.signal("pwrite"),
+            "input wire [2:0] " + self.signal("pprot"),
+            f"input wire [{self.addr_width-1}:0] " + self.signal("paddr"),
+            f"input wire [{self.data_width-1}:0] " + self.signal("pwdata"),
+            f"input wire [{self.data_width_bytes-1}:0] " + self.signal("pstrb"),
+            "output logic " + self.signal("pready"),
+            f"output logic [{self.data_width-1}:0] " + self.signal("prdata"),
+            "output logic " + self.signal("pslverr"),
+        ]
+        return ",\n".join(lines)
+
+    def signal(self, name:str) -> str:
+        return "s_apb_" + name

src/peakrdl_regblock/cpuif/apb4/apb4_tmpl.sv

@@ -0,0 +1,39 @@
+// Request
+logic is_active;
+always_ff {{get_always_ff_event(cpuif.reset)}} begin
+    if({{get_resetsignal(cpuif.reset)}}) begin
+        is_active <= '0;
+        cpuif_req <= '0;
+        cpuif_req_is_wr <= '0;
+        cpuif_addr <= '0;
+        cpuif_wr_data <= '0;
+        cpuif_wr_biten <= '0;
+    end else begin
+        if(~is_active) begin
+            if({{cpuif.signal("psel")}}) begin
+                is_active <= '1;
+                cpuif_req <= '1;
+                cpuif_req_is_wr <= {{cpuif.signal("pwrite")}};
+                {%- if cpuif.data_width == 8 %}
+                cpuif_addr <= {{cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:0];
+                {%- else %}
+                cpuif_addr <= { {{-cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width//8)}}], {{clog2(cpuif.data_width//8)}}'b0};
+                {%- endif %}
+                cpuif_wr_data <= {{cpuif.signal("pwdata")}};
+                for(int i=0; i<{{cpuif.data_width_bytes}}; i++) begin
+                    cpuif_wr_biten[i*8 +: 8] <= {8{ {{-cpuif.signal("pstrb")}}[i]}};
+                end
+            end
+        end else begin
+            cpuif_req <= '0;
+            if(cpuif_rd_ack || cpuif_wr_ack) begin
+                is_active <= '0;
+            end
+        end
+    end
+end
+
+// Response
+assign {{cpuif.signal("pready")}} = cpuif_rd_ack | cpuif_wr_ack;
+assign {{cpuif.signal("prdata")}} = cpuif_rd_data;
+assign {{cpuif.signal("pslverr")}} = cpuif_rd_err | cpuif_wr_err;

src/peakrdl_regblock/exporter.py

@@ -11,7 +11,7 @@ from .readback import Readback
 from .identifier_filter import kw_filter as kwf
 
 from .cpuif import CpuifBase
-from .cpuif.apb3 import APB3_Cpuif
+from .cpuif.apb4 import APB4_Cpuif
 from .hwif import Hwif
 from .utils import get_always_ff_event
 from .scan_design import DesignScanner
@@ -57,7 +57,7 @@ class RegblockExporter:
             Output includes two files: a module definition and package definition.
         cpuif_cls: :class:`peakrdl_regblock.cpuif.CpuifBase`
             Specify the class type that implements the CPU interface of your choice.
-            Defaults to AMBA APB3.
+            Defaults to AMBA APB4.
         module_name: str
             Override the SystemVerilog module name. By default, the module name
             is the top-level node's name.
@@ -100,7 +100,7 @@ class RegblockExporter:
             self.top_node = node
 
 
-        cpuif_cls = kwargs.pop("cpuif_cls", None) or APB3_Cpuif # type: Type[CpuifBase]
+        cpuif_cls = kwargs.pop("cpuif_cls", None) or APB4_Cpuif # type: Type[CpuifBase]
         module_name = kwargs.pop("module_name", None) or kwf(self.top_node.inst_name) # type: str
         package_name = kwargs.pop("package_name", None) or (module_name + "_pkg") # type: str
         reuse_hwif_typedefs = kwargs.pop("reuse_hwif_typedefs", True) # type: bool