Add APB4 cpuif

tests/lib/base_testcase.py

@@ -11,7 +11,7 @@ from systemrdl import RDLCompiler
 
 from peakrdl_regblock import RegblockExporter
 from .cpuifs.base import CpuifTestMode
-from .cpuifs.apb3 import APB3
+from .cpuifs.apb4 import APB4
 
 
 class BaseTestCase(unittest.TestCase):
@@ -28,7 +28,7 @@ class BaseTestCase(unittest.TestCase):
     rdl_elab_params = {}
 
     #: Define what CPUIF to use for this testcase
-    cpuif = APB3() # type: CpuifTestMode
+    cpuif = APB4() # type: CpuifTestMode
 
     # Other exporter args:
     retime_read_fanin = False

tests/lib/cpuifs/apb4/__init__.py

@@ -0,0 +1,18 @@
+from ..base import CpuifTestMode
+
+from peakrdl_regblock.cpuif.apb4 import APB4_Cpuif, APB4_Cpuif_flattened
+
+class APB4(CpuifTestMode):
+    cpuif_cls = APB4_Cpuif
+    rtl_files = [
+        "apb4_intf.sv",
+    ]
+    tb_files = [
+        "apb4_intf.sv",
+        "apb4_intf_driver.sv",
+    ]
+    tb_template = "tb_inst.sv"
+
+class FlatAPB4(APB4):
+    cpuif_cls = APB4_Cpuif_flattened
+    rtl_files = []

tests/lib/cpuifs/apb4/apb4_intf.sv

@@ -0,0 +1,46 @@
+interface apb4_intf #(
+    parameter DATA_WIDTH = 32,
+    parameter ADDR_WIDTH = 32
+);
+    // Command
+    logic PSEL;
+    logic PENABLE;
+    logic PWRITE;
+    logic [2:0] PPROT;
+    logic [ADDR_WIDTH-1:0] PADDR;
+    logic [DATA_WIDTH-1:0] PWDATA;
+    logic [DATA_WIDTH/8-1:0] PSTRB;
+
+    // Response
+    logic [DATA_WIDTH-1:0] PRDATA;
+    logic PREADY;
+    logic PSLVERR;
+
+    modport master (
+        output PSEL,
+        output PENABLE,
+        output PWRITE,
+        output PPROT,
+        output PADDR,
+        output PWDATA,
+        output PSTRB,
+
+        input PRDATA,
+        input PREADY,
+        input PSLVERR
+    );
+
+    modport slave (
+        input PSEL,
+        input PENABLE,
+        input PWRITE,
+        input PPROT,
+        input PADDR,
+        input PWDATA,
+        input PSTRB,
+
+        output PRDATA,
+        output PREADY,
+        output PSLVERR
+    );
+endinterface

tests/lib/cpuifs/apb4/apb4_intf_driver.sv

@@ -0,0 +1,128 @@
+interface apb4_intf_driver #(
+        parameter DATA_WIDTH = 32,
+        parameter ADDR_WIDTH = 32
+    )(
+        input wire clk,
+        input wire rst,
+        apb4_intf.master m_apb
+    );
+
+    timeunit 1ps;
+    timeprecision 1ps;
+
+    logic PSEL;
+    logic PENABLE;
+    logic PWRITE;
+    logic [2:0] PPROT;
+    logic [ADDR_WIDTH-1:0] PADDR;
+    logic [DATA_WIDTH-1:0] PWDATA;
+    logic [DATA_WIDTH/8-1:0] PSTRB;
+    logic [DATA_WIDTH-1:0] PRDATA;
+    logic PREADY;
+    logic PSLVERR;
+
+    assign m_apb.PSEL = PSEL;
+    assign m_apb.PENABLE = PENABLE;
+    assign m_apb.PWRITE = PWRITE;
+    assign m_apb.PPROT = PPROT;
+    assign m_apb.PADDR = PADDR;
+    assign m_apb.PWDATA = PWDATA;
+    assign m_apb.PSTRB = PSTRB;
+    assign PRDATA = m_apb.PRDATA;
+    assign PREADY = m_apb.PREADY;
+    assign PSLVERR = m_apb.PSLVERR;
+
+    default clocking cb @(posedge clk);
+        default input #1step output #1;
+        output PSEL;
+        output PENABLE;
+        output PWRITE;
+        output PPROT;
+        output PADDR;
+        output PWDATA;
+        output PSTRB;
+        input PRDATA;
+        input PREADY;
+        input PSLVERR;
+    endclocking
+
+    task automatic reset();
+        cb.PSEL <= '0;
+        cb.PENABLE <= '0;
+        cb.PWRITE <= '0;
+        cb.PPROT <= '0;
+        cb.PADDR <= '0;
+        cb.PWDATA <= '0;
+        cb.PSTRB <= '0;
+    endtask
+
+    semaphore txn_mutex = new(1);
+
+    task automatic write(logic [ADDR_WIDTH-1:0] addr, logic [DATA_WIDTH-1:0] data);
+        txn_mutex.get();
+        ##0;
+
+        // Initiate transfer
+        cb.PSEL <= '1;
+        cb.PENABLE <= '0;
+        cb.PWRITE <= '1;
+        cb.PPROT <= '0;
+        cb.PADDR <= addr;
+        cb.PWDATA <= data;
+        cb.PSTRB <= '1;
+        @(cb);
+
+        // active phase
+        cb.PENABLE <= '1;
+        @(cb);
+
+        // Wait for response
+        while(cb.PREADY !== 1'b1) @(cb);
+        reset();
+        txn_mutex.put();
+    endtask
+
+    task automatic read(logic [ADDR_WIDTH-1:0] addr, output logic [DATA_WIDTH-1:0] data);
+        txn_mutex.get();
+        ##0;
+
+        // Initiate transfer
+        cb.PSEL <= '1;
+        cb.PENABLE <= '0;
+        cb.PWRITE <= '0;
+        cb.PPROT <= '0;
+        cb.PADDR <= addr;
+        cb.PWDATA <= '0;
+        cb.PSTRB <= '0;
+        @(cb);
+
+        // active phase
+        cb.PENABLE <= '1;
+        @(cb);
+
+        // Wait for response
+        while(cb.PREADY !== 1'b1) @(cb);
+        assert(!$isunknown(cb.PRDATA)) else $error("Read from 0x%0x returned X's on PRDATA", addr);
+        assert(!$isunknown(cb.PSLVERR)) else $error("Read from 0x%0x returned X's on PSLVERR", addr);
+        data = cb.PRDATA;
+        reset();
+        txn_mutex.put();
+    endtask
+
+    task automatic assert_read(logic [ADDR_WIDTH-1:0] addr, logic [DATA_WIDTH-1:0] expected_data, logic [DATA_WIDTH-1:0] mask = '1);
+        logic [DATA_WIDTH-1:0] data;
+        read(addr, data);
+        data &= mask;
+        assert(data == expected_data) else $error("Read from 0x%x returned 0x%x. Expected 0x%x", addr, data, expected_data);
+    endtask
+
+    initial begin
+        reset();
+    end
+
+    initial forever begin
+        @cb;
+        if(!rst) assert(!$isunknown(cb.PREADY)) else $error("Saw X on PREADY!");
+    end
+
+endinterface

tests/lib/cpuifs/apb4/tb_inst.sv

@@ -0,0 +1,36 @@
+{% sv_line_anchor %}
+apb4_intf #(
+    .DATA_WIDTH({{exporter.cpuif.data_width}}),
+    .ADDR_WIDTH({{exporter.cpuif.addr_width}})
+) s_apb();
+apb4_intf_driver #(
+    .DATA_WIDTH({{exporter.cpuif.data_width}}),
+    .ADDR_WIDTH({{exporter.cpuif.addr_width}})
+) cpuif (
+    .clk(clk),
+    .rst(rst),
+    .m_apb(s_apb)
+);
+{% if type(cpuif).__name__.startswith("Flat") %}
+{% sv_line_anchor %}
+wire s_apb_psel;
+wire s_apb_penable;
+wire s_apb_pwrite;
+wire [2:0] s_apb_pprot;
+wire [{{exporter.cpuif.addr_width - 1}}:0] s_apb_paddr;
+wire [{{exporter.cpuif.data_width - 1}}:0] s_apb_pwdata;
+wire [{{exporter.cpuif.data_width_bytes - 1}}:0] s_apb_pstrb;
+wire s_apb_pready;
+wire [{{exporter.cpuif.data_width - 1}}:0] s_apb_prdata;
+wire s_apb_pslverr;
+assign s_apb_psel = s_apb.PSEL;
+assign s_apb_penable = s_apb.PENABLE;
+assign s_apb_pwrite = s_apb.PWRITE;
+assign s_apb_pprot = s_apb.PPROT;
+assign s_apb_paddr = s_apb.PADDR;
+assign s_apb_pwdata = s_apb.PWDATA;
+assign s_apb_pstrb = s_apb.PSTRB;
+assign s_apb.PREADY = s_apb_pready;
+assign s_apb.PRDATA = s_apb_prdata;
+assign s_apb.PSLVERR = s_apb_pslverr;
+{% endif %}

tests/lib/test_params.py

@@ -1,6 +1,7 @@
 from itertools import product
 
 from .cpuifs.apb3 import APB3, FlatAPB3
+from .cpuifs.apb4 import APB4, FlatAPB4
 from .cpuifs.axi4lite import AXI4Lite, FlatAXI4Lite
 from .cpuifs.passthrough import Passthrough
 
@@ -8,6 +9,8 @@ from .cpuifs.passthrough import Passthrough
 all_cpuif = [
     APB3(),
     FlatAPB3(),
+    APB4(),
+    FlatAPB4(),
     AXI4Lite(),
     FlatAXI4Lite(),
     Passthrough(),