Fix bug where small designs with 3 or less sw readable addresses and readback retiming enabled generate incorrect output.

2023-05-14 22:46:16 -07:00
parent b8516a19c3
commit 3e691cb5fb
4 changed files with 25 additions and 13 deletions
--- a/src/peakrdl_regblock/module_tmpl.sv
+++ b/src/peakrdl_regblock/module_tmpl.sv
@@ -226,7 +226,7 @@ module {{ds.module_name}} (
    logic readback_err;
    logic readback_done;
    logic [{{cpuif.data_width-1}}:0] readback_data;
-    {{readback.get_implementation()|indent}}
+    {{readback_implementation|indent}}
 {% if ds.retime_read_response %}
    always_ff {{get_always_ff_event(cpuif.reset)}} begin
        if({{get_resetsignal(cpuif.reset)}}) begin