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Simplify stickybit implementation for single-bit fields to not create redundant expression. #127

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This commit is contained in:
Alex Mykyta
2025-03-07 19:39:57 -08:00
parent 6430dd4914
commit 3ed2e1f891
1 changed files with 55 additions and 28 deletions
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27
src/peakrdl_regblock/field_logic/hw_interrupts.py
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@@ -46,9 +46,18 @@ class Stickybit(NextStateConditional):
def get_predicate(self, field: 'FieldNode') -> str:
F = self.exp.hwif.get_input_identifier(field)
if field.width == 1:
return str(F)
else:
return f"{F} != '0"
def get_assignments(self, field: 'FieldNode') -> List[str]:
if field.width == 1:
return [
"next_c = '1;",
"load_next_c = '1;",
]
else:
I = self.exp.hwif.get_input_identifier(field)
R = self.exp.field_logic.get_storage_identifier(field)
return [
@@ -74,6 +83,12 @@ class PosedgeStickybit(NextStateConditional):
return f"(~{Iq} & {I}) != '0"
def get_assignments(self, field: 'FieldNode') -> List[str]:
if field.width == 1:
return [
"next_c = '1;",
"load_next_c = '1;",
]
else:
I = self.exp.hwif.get_input_identifier(field)
Iq = self.exp.field_logic.get_next_q_identifier(field)
R = self.exp.field_logic.get_storage_identifier(field)
@@ -100,6 +115,12 @@ class NegedgeStickybit(NextStateConditional):
return f"({Iq} & ~{I}) != '0"
def get_assignments(self, field: 'FieldNode') -> List[str]:
if field.width == 1:
return [
"next_c = '1;",
"load_next_c = '1;",
]
else:
I = self.exp.hwif.get_input_identifier(field)
Iq = self.exp.field_logic.get_next_q_identifier(field)
R = self.exp.field_logic.get_storage_identifier(field)
@@ -126,6 +147,12 @@ class BothedgeStickybit(NextStateConditional):
return f"{Iq} != {I}"
def get_assignments(self, field: 'FieldNode') -> List[str]:
if field.width == 1:
return [
"next_c = '1;",
"load_next_c = '1;",
]
else:
I = self.exp.hwif.get_input_identifier(field)
Iq = self.exp.field_logic.get_next_q_identifier(field)
R = self.exp.field_logic.get_storage_identifier(field)