Type hinting cleanup
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@@ -99,6 +99,7 @@ class NextStateConditional:
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<field>.next = <next value>
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<field>.load_next = '1;
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"""
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raise NotImplementedError
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def get_extra_combo_signals(self, field: 'FieldNode') -> List[SVLogic]:
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"""
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@@ -46,7 +46,7 @@ class WEWrite(AlwaysWrite):
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def is_match(self, field: 'FieldNode') -> bool:
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return (
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field.is_hw_writable
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and field.get_property('we')
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and bool(field.get_property('we'))
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)
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def get_predicate(self, field: 'FieldNode') -> str:
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@@ -64,7 +64,7 @@ class WELWrite(AlwaysWrite):
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def is_match(self, field: 'FieldNode') -> bool:
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return (
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field.is_hw_writable
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and field.get_property('wel')
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and bool(field.get_property('wel'))
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)
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def get_predicate(self, field: 'FieldNode') -> str:
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@@ -1,4 +1,4 @@
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from typing import TYPE_CHECKING, List
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from typing import TYPE_CHECKING, List, Optional
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from systemrdl.rdltypes import OnWriteType
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@@ -10,7 +10,7 @@ if TYPE_CHECKING:
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# TODO: implement sw=w1 "write once" fields
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class _OnWrite(NextStateConditional):
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onwritetype = None # type: OnWriteType
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onwritetype: Optional[OnWriteType] = None
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def is_match(self, field: 'FieldNode') -> bool:
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return field.is_sw_writable and field.get_property('onwrite') == self.onwritetype
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