Add 'rd_swacc' and 'wr_swacc' UDPs. #21

This commit is contained in:
Alex Mykyta
2022-11-09 21:22:59 -08:00
parent 17afaf13ff
commit 489b4d1310
17 changed files with 243 additions and 12 deletions

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@@ -1 +1 @@
__version__ = "0.8.0"
__version__ = "0.9.0"

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@@ -161,6 +161,10 @@ class Dereferencer:
return self.field_logic.get_swacc_identifier(field)
if prop_name == "swmod":
return self.field_logic.get_swmod_identifier(field)
if prop_name == "rd_swacc":
return self.field_logic.get_rd_swacc_identifier(field)
if prop_name == "wr_swacc":
return self.field_logic.get_wr_swacc_identifier(field)
# translate aliases

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@@ -193,6 +193,30 @@ class FieldLogic:
strb = self.exp.dereferencer.get_access_strobe(field)
return strb
def get_rd_swacc_identifier(self, field: 'FieldNode') -> str:
"""
Asserted when field is software accessed (read)
"""
buffer_reads = field.parent.get_property('buffer_reads')
if buffer_reads:
rstrb = self.exp.read_buffering.get_trigger(field.parent)
return rstrb
else:
strb = self.exp.dereferencer.get_access_strobe(field)
return f"{strb} && !decoded_req_is_wr"
def get_wr_swacc_identifier(self, field: 'FieldNode') -> str:
"""
Asserted when field is software accessed (write)
"""
buffer_writes = field.parent.get_property('buffer_writes')
if buffer_writes:
wstrb = self.exp.write_buffering.get_write_strobe(field)
return wstrb
else:
strb = self.exp.dereferencer.get_access_strobe(field)
return f"{strb} && decoded_req_is_wr"
def get_swmod_identifier(self, field: 'FieldNode') -> str:
"""
Asserted when field is modified by software (written or read with a

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@@ -224,20 +224,33 @@ class FieldLogicGenerator(RDLForLoopGenerator):
f"assign {output_identifier} = {value};"
)
# Software access strobes
if node.get_property('swmod'):
output_identifier = self.exp.hwif.get_implied_prop_output_identifier(node, "swmod")
value = self.field_logic.get_swmod_identifier(node)
self.add_content(
f"assign {output_identifier} = {value};"
)
if node.get_property('swacc'):
output_identifier = self.exp.hwif.get_implied_prop_output_identifier(node, "swacc")
value = self.field_logic.get_swacc_identifier(node)
self.add_content(
f"assign {output_identifier} = {value};"
)
if node.get_property('rd_swacc'):
output_identifier = self.exp.hwif.get_implied_prop_output_identifier(node, "rd_swacc")
value = self.field_logic.get_rd_swacc_identifier(node)
self.add_content(
f"assign {output_identifier} = {value};"
)
if node.get_property('wr_swacc'):
output_identifier = self.exp.hwif.get_implied_prop_output_identifier(node, "wr_swacc")
value = self.field_logic.get_wr_swacc_identifier(node)
self.add_content(
f"assign {output_identifier} = {value};"
)
# Counter thresholds
if node.get_property('incrthreshold') is not False: # (explicitly not False. Not 0)
output_identifier = self.exp.hwif.get_implied_prop_output_identifier(node, "incrthreshold")
value = self.field_logic.get_field_combo_identifier(node, 'incrthreshold')
@@ -251,6 +264,7 @@ class FieldLogicGenerator(RDLForLoopGenerator):
f"assign {output_identifier} = {value};"
)
# Counter events
if node.get_property('overflow'):
output_identifier = self.exp.hwif.get_implied_prop_output_identifier(node, "overflow")
value = self.field_logic.get_field_combo_identifier(node, 'overflow')

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@@ -190,6 +190,7 @@ class Hwif:
assert prop in {
"anded", "ored", "xored", "swmod", "swacc",
"incrthreshold", "decrthreshold", "overflow", "underflow",
"rd_swacc", "wr_swacc",
}
elif isinstance(node, RegNode):
assert prop in {

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@@ -128,7 +128,7 @@ class OutputStructGenerator_Hier(HWIFStructGenerator):
self.add_member("value", node.width)
# Generate output bit signals enabled via property
for prop_name in ["anded", "ored", "xored", "swmod", "swacc", "overflow", "underflow"]:
for prop_name in ["anded", "ored", "xored", "swmod", "swacc", "overflow", "underflow", "rd_swacc", "wr_swacc"]:
if node.get_property(prop_name):
self.add_member(prop_name)

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@@ -0,0 +1,12 @@
from .rw_buffering import BufferWrites, WBufferTrigger
from .rw_buffering import BufferReads, RBufferTrigger
from .extended_swacc import ReadSwacc, WriteSwacc
ALL_UDPS = [
BufferWrites,
WBufferTrigger,
BufferReads,
RBufferTrigger,
ReadSwacc,
WriteSwacc,
]

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@@ -0,0 +1,23 @@
from typing import TYPE_CHECKING, Any
from systemrdl.udp import UDPDefinition
from systemrdl.component import Field
if TYPE_CHECKING:
from systemrdl.node import Node
class ReadSwacc(UDPDefinition):
name = "rd_swacc"
valid_components = {Field}
valid_type = bool
def get_unassigned_default(self, node: 'Node') -> Any:
return False
class WriteSwacc(UDPDefinition):
name = "wr_swacc"
valid_components = {Field}
valid_type = bool
def get_unassigned_default(self, node: 'Node') -> Any:
return False

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@@ -118,12 +118,3 @@ class RBufferTrigger(xBufferTrigger):
if node.get_property('buffer_reads'):
return node
return None
ALL_UDPS = [
BufferWrites,
WBufferTrigger,
BufferReads,
RBufferTrigger,
]