Add 'rd_swacc' and 'wr_swacc' UDPs. #21
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@@ -1 +1 @@
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__version__ = "0.8.0"
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__version__ = "0.9.0"
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@@ -161,6 +161,10 @@ class Dereferencer:
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return self.field_logic.get_swacc_identifier(field)
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if prop_name == "swmod":
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return self.field_logic.get_swmod_identifier(field)
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if prop_name == "rd_swacc":
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return self.field_logic.get_rd_swacc_identifier(field)
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if prop_name == "wr_swacc":
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return self.field_logic.get_wr_swacc_identifier(field)
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# translate aliases
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@@ -193,6 +193,30 @@ class FieldLogic:
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strb = self.exp.dereferencer.get_access_strobe(field)
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return strb
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def get_rd_swacc_identifier(self, field: 'FieldNode') -> str:
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"""
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Asserted when field is software accessed (read)
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"""
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buffer_reads = field.parent.get_property('buffer_reads')
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if buffer_reads:
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rstrb = self.exp.read_buffering.get_trigger(field.parent)
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return rstrb
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else:
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strb = self.exp.dereferencer.get_access_strobe(field)
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return f"{strb} && !decoded_req_is_wr"
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def get_wr_swacc_identifier(self, field: 'FieldNode') -> str:
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"""
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Asserted when field is software accessed (write)
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"""
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buffer_writes = field.parent.get_property('buffer_writes')
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if buffer_writes:
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wstrb = self.exp.write_buffering.get_write_strobe(field)
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return wstrb
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else:
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strb = self.exp.dereferencer.get_access_strobe(field)
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return f"{strb} && decoded_req_is_wr"
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def get_swmod_identifier(self, field: 'FieldNode') -> str:
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"""
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Asserted when field is modified by software (written or read with a
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@@ -224,20 +224,33 @@ class FieldLogicGenerator(RDLForLoopGenerator):
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f"assign {output_identifier} = {value};"
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)
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# Software access strobes
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if node.get_property('swmod'):
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output_identifier = self.exp.hwif.get_implied_prop_output_identifier(node, "swmod")
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value = self.field_logic.get_swmod_identifier(node)
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self.add_content(
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f"assign {output_identifier} = {value};"
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)
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if node.get_property('swacc'):
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output_identifier = self.exp.hwif.get_implied_prop_output_identifier(node, "swacc")
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value = self.field_logic.get_swacc_identifier(node)
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self.add_content(
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f"assign {output_identifier} = {value};"
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)
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if node.get_property('rd_swacc'):
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output_identifier = self.exp.hwif.get_implied_prop_output_identifier(node, "rd_swacc")
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value = self.field_logic.get_rd_swacc_identifier(node)
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self.add_content(
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f"assign {output_identifier} = {value};"
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)
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if node.get_property('wr_swacc'):
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output_identifier = self.exp.hwif.get_implied_prop_output_identifier(node, "wr_swacc")
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value = self.field_logic.get_wr_swacc_identifier(node)
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self.add_content(
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f"assign {output_identifier} = {value};"
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)
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# Counter thresholds
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if node.get_property('incrthreshold') is not False: # (explicitly not False. Not 0)
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output_identifier = self.exp.hwif.get_implied_prop_output_identifier(node, "incrthreshold")
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value = self.field_logic.get_field_combo_identifier(node, 'incrthreshold')
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@@ -251,6 +264,7 @@ class FieldLogicGenerator(RDLForLoopGenerator):
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f"assign {output_identifier} = {value};"
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)
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# Counter events
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if node.get_property('overflow'):
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output_identifier = self.exp.hwif.get_implied_prop_output_identifier(node, "overflow")
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value = self.field_logic.get_field_combo_identifier(node, 'overflow')
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@@ -190,6 +190,7 @@ class Hwif:
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assert prop in {
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"anded", "ored", "xored", "swmod", "swacc",
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"incrthreshold", "decrthreshold", "overflow", "underflow",
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"rd_swacc", "wr_swacc",
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}
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elif isinstance(node, RegNode):
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assert prop in {
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@@ -128,7 +128,7 @@ class OutputStructGenerator_Hier(HWIFStructGenerator):
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self.add_member("value", node.width)
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# Generate output bit signals enabled via property
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for prop_name in ["anded", "ored", "xored", "swmod", "swacc", "overflow", "underflow"]:
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for prop_name in ["anded", "ored", "xored", "swmod", "swacc", "overflow", "underflow", "rd_swacc", "wr_swacc"]:
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if node.get_property(prop_name):
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self.add_member(prop_name)
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12
src/peakrdl_regblock/udps/__init__.py
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12
src/peakrdl_regblock/udps/__init__.py
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@@ -0,0 +1,12 @@
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from .rw_buffering import BufferWrites, WBufferTrigger
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from .rw_buffering import BufferReads, RBufferTrigger
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from .extended_swacc import ReadSwacc, WriteSwacc
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ALL_UDPS = [
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BufferWrites,
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WBufferTrigger,
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BufferReads,
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RBufferTrigger,
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ReadSwacc,
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WriteSwacc,
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]
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23
src/peakrdl_regblock/udps/extended_swacc.py
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23
src/peakrdl_regblock/udps/extended_swacc.py
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@@ -0,0 +1,23 @@
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from typing import TYPE_CHECKING, Any
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from systemrdl.udp import UDPDefinition
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from systemrdl.component import Field
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if TYPE_CHECKING:
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from systemrdl.node import Node
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class ReadSwacc(UDPDefinition):
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name = "rd_swacc"
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valid_components = {Field}
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valid_type = bool
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def get_unassigned_default(self, node: 'Node') -> Any:
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return False
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class WriteSwacc(UDPDefinition):
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name = "wr_swacc"
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valid_components = {Field}
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valid_type = bool
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def get_unassigned_default(self, node: 'Node') -> Any:
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return False
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@@ -118,12 +118,3 @@ class RBufferTrigger(xBufferTrigger):
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if node.get_property('buffer_reads'):
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return node
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return None
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ALL_UDPS = [
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BufferWrites,
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WBufferTrigger,
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BufferReads,
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RBufferTrigger,
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]
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