Add 'rd_swacc' and 'wr_swacc' UDPs. #21

src/peakrdl_regblock/hwif/__init__.py

@@ -190,6 +190,7 @@ class Hwif:
             assert prop in {
                 "anded", "ored", "xored", "swmod", "swacc",
                 "incrthreshold", "decrthreshold", "overflow", "underflow",
+                "rd_swacc", "wr_swacc",
             }
         elif isinstance(node, RegNode):
             assert prop in {

src/peakrdl_regblock/hwif/generators.py

@@ -128,7 +128,7 @@ class OutputStructGenerator_Hier(HWIFStructGenerator):
             self.add_member("value", node.width)
 
         # Generate output bit signals enabled via property
-        for prop_name in ["anded", "ored", "xored", "swmod", "swacc", "overflow", "underflow"]:
+        for prop_name in ["anded", "ored", "xored", "swmod", "swacc", "overflow", "underflow", "rd_swacc", "wr_swacc"]:
             if node.get_property(prop_name):
                 self.add_member(prop_name)