From 48adbe142e3321151613ee91f2f5878a7e4297bd Mon Sep 17 00:00:00 2001 From: Alex Mykyta Date: Mon, 27 Dec 2021 18:09:28 -0800 Subject: [PATCH] doc --- docs/dev_notes/Interrupts | 18 ------------------ docs/dev_notes/Validation Needed | 14 +++++++++++--- docs/props/rhs_props.rst | 8 ++++---- 3 files changed, 15 insertions(+), 25 deletions(-) delete mode 100644 docs/dev_notes/Interrupts diff --git a/docs/dev_notes/Interrupts b/docs/dev_notes/Interrupts deleted file mode 100644 index e21614e..0000000 --- a/docs/dev_notes/Interrupts +++ /dev/null @@ -1,18 +0,0 @@ - -Interrupts seem to be pretty well-described. -Basically... - - - If a register contains one or more fields that use the intr property, - then it is implied to be an interrupt register - --> Add RegNode.has_intr and RegNode.has_halt properties? - - This register implies that there is an output irq signal that is propagated to the top, and it is the OR of all interrupt field bits - - BUT in the multilevel interrupt example, perhaps this output gets suppressed? - Suppress the output signal if Reg->intr gets referenced, since this means - the user is doing a multi-level interrupt. - This means that the register's interrupt signal is "consumed" by a second-level interrupt register - - - WTF about the "halt" concept? - I assume this does NOT auto-imply an output? - Mayby only imply a default halt output if: - - an interrupt register has fields that use haltenable/haltmask - - AND the interrupt register's reg->halt has not been referenced \ No newline at end of file diff --git a/docs/dev_notes/Validation Needed b/docs/dev_notes/Validation Needed index 6fc6317..df0f8a4 100644 --- a/docs/dev_notes/Validation Needed +++ b/docs/dev_notes/Validation Needed @@ -95,13 +95,21 @@ X Signals marked as field_reset or cpuif_reset need to have activehigh/activelow specified. (8.2.1-d states that activehigh/low does not have an implied default state if unset!) Also applies to signals referenced by resetsignal +X incrvalue/decrvalue needs to be the same or narrower than counter itself + +X field shall be hw writable if "next" is assigned. + +X sticky=true + "(posedge|negedge|bothedge) intr" + Edge-sensitivty doesnt make sense for full-field stickiness + +X we/wel + implied or explicit "sticky"/"stickybit" + we/wel modifier doesnt make sense here. + ! hwclr/hwset/we/wel probably shouldn't be able to reference itself y->hwclr = y; y->we = y; ... it works, but should it be allowed? Seems like user-error -X incrvalue/decrvalue needs to be the same or narrower than counter itself - ! counter field that saturates should not set overflow counter; incrsaturate; overflow; counter; decrsaturate; underflow; @@ -113,7 +121,7 @@ X incrvalue/decrvalue needs to be the same or narrower than counter itself ! incrwidth/decrwidth must be between 1 and the width of the counter -X field shall be hw writable if "next" is assigned. +! Illegal to use enable/mask/haltenable/haltmask on non-intr fields ================================================================================ Things that need validation by this exporter diff --git a/docs/props/rhs_props.rst b/docs/props/rhs_props.rst index 51e33ef..51671eb 100644 --- a/docs/props/rhs_props.rst +++ b/docs/props/rhs_props.rst @@ -186,6 +186,10 @@ field -> enable ^^^^^^^^^^^^^^^ |EX| +field -> mask +^^^^^^^^^^^^^ +|EX| + field -> haltenable ^^^^^^^^^^^^^^^^^^^ |EX| @@ -194,10 +198,6 @@ field -> haltmask ^^^^^^^^^^^^^^^^^ |EX| -field -> mask -^^^^^^^^^^^^^ -|EX| - --------------------------------------------------------------------------------