diff --git a/setup.py b/setup.py
index 3dd9481..c182186 100644
--- a/setup.py
+++ b/setup.py
@@ -24,7 +24,7 @@ setuptools.setup(
     include_package_data=True,
     python_requires='>=3.6',
     install_requires=[
-        "systemrdl-compiler>=1.22.0",
+        "systemrdl-compiler>=1.23.0",
         "Jinja2>=2.11",
     ],
     entry_points = {
diff --git a/src/peakrdl_regblock/scan_design.py b/src/peakrdl_regblock/scan_design.py
index e159fb8..d48db88 100644
--- a/src/peakrdl_regblock/scan_design.py
+++ b/src/peakrdl_regblock/scan_design.py
@@ -118,6 +118,7 @@ class DesignScanner(RDLListener):
             )
             # Do not inspect external components. None of my business
             return WalkerAction.SkipDescendants
+        return None
 
     def enter_Signal(self, node: 'SignalNode') -> None:
         # If encountering a CPUIF reset that is nested within the register model,