bslathi19/PeakRDL-regblock
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Fix lint issue

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This commit is contained in:
Alex Mykyta
2022-09-12 21:35:37 -07:00
parent e2d6fc1c60
commit 4bee895c71
2 changed files with 2 additions and 1 deletions
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2
setup.py
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@@ -24,7 +24,7 @@ setuptools.setup(
include_package_data=True, include_package_data=True,
python_requires='>=3.6', python_requires='>=3.6',
install_requires=[ install_requires=[
"systemrdl-compiler>=1.22.0", "systemrdl-compiler>=1.23.0",
"Jinja2>=2.11", "Jinja2>=2.11",
], ],
entry_points = { entry_points = {

1
src/peakrdl_regblock/scan_design.py
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@@ -118,6 +118,7 @@ class DesignScanner(RDLListener):
) )
# Do not inspect external components. None of my business # Do not inspect external components. None of my business
return WalkerAction.SkipDescendants return WalkerAction.SkipDescendants
return None
def enter_Signal(self, node: 'SignalNode') -> None: def enter_Signal(self, node: 'SignalNode') -> None:
# If encountering a CPUIF reset that is nested within the register model, # If encountering a CPUIF reset that is nested within the register model,