From 4c819b4bcbc0984332a8758a4352c11e63712c89 Mon Sep 17 00:00:00 2001 From: Alex Mykyta Date: Fri, 8 Aug 2025 17:05:58 -0700 Subject: [PATCH] fix doc phrasing --- docs/rdl_features/external.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/rdl_features/external.rst b/docs/rdl_features/external.rst index 2032b5b..15d275e 100644 --- a/docs/rdl_features/external.rst +++ b/docs/rdl_features/external.rst @@ -17,9 +17,9 @@ Things you should know * By default external ``hwif_out`` signals are driven combinationally. An optional output retiming stage can be enabled if needed. * Due to the uncertain access latency of external components, the regblock will - always enforce that only one outstanding transaction to an external component - at a time. This is enforced even if the CPUIF is capable of pipelined accesses - such as AXI4-Lite. + only issue one outstanding transaction to an external component at a time. + This is enforced even if the CPUIF is capable of pipelined accesses such as + AXI4-Lite. External Registers