Add support for CPUIFs to have parameters #80

2024-03-29 22:39:45 -07:00
parent f25ba60bfc
commit 4dfd9b10d6
2 changed files with 12 additions and 2 deletions
--- a/src/peakrdl_regblock/module_tmpl.sv
+++ b/src/peakrdl_regblock/module_tmpl.sv
@@ -1,7 +1,10 @@
 // Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
 //  https://github.com/SystemRDL/PeakRDL-regblock

-module {{ds.module_name}} (
+module {{ds.module_name}}
+    {%- if cpuif.parameters %} #(
+        {{",\n        ".join(cpuif.parameters)}}
+    ) {%- endif %} (
        input wire clk,
        input wire {{default_resetsignal_name}},