Add support for CPUIFs to have parameters #80

src/peakrdl_regblock/cpuif/base.py

@@ -1,4 +1,4 @@
-from typing import TYPE_CHECKING
+from typing import TYPE_CHECKING, List
 import inspect
 import os
 
@@ -34,6 +34,13 @@ class CpuifBase:
     def port_declaration(self) -> str:
         raise NotImplementedError()
 
+    @property
+    def parameters(self) -> List[str]:
+        """
+        Optional list of additional parameters this CPU interface provides to
+        the module's definition
+        """
+        return []
 
     def _get_template_path_class_dir(self) -> str:
         """

src/peakrdl_regblock/module_tmpl.sv

@@ -1,7 +1,10 @@
 // Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
 //  https://github.com/SystemRDL/PeakRDL-regblock
 
-module {{ds.module_name}} (
+module {{ds.module_name}}
+    {%- if cpuif.parameters %} #(
+        {{",\n        ".join(cpuif.parameters)}}
+    ) {%- endif %} (
         input wire clk,
         input wire {{default_resetsignal_name}},