Use sized integer literals if bit width exceeds 32-bits. #43

src/peakrdl_regblock/addr_decode.py

@@ -3,7 +3,7 @@ from typing import TYPE_CHECKING, Union, List, Optional
 from systemrdl.node import FieldNode, RegNode
 from systemrdl.walker import WalkerAction
 
-from .utils import get_indexed_path
+from .utils import get_indexed_path, get_sv_int
 from .struct_generator import RDLStructGenerator
 from .forloop_generator import RDLForLoopGenerator
 from .identifier_filter import kw_filter as kwf
@@ -137,7 +137,7 @@ class DecodeLogicGenerator(RDLForLoopGenerator):
         super().__init__()
 
         # List of address strides for each dimension
-        self._array_stride_stack = [] # type: List[List[int]]
+        self._array_stride_stack = [] # type: List[int]
 
 
     def enter_AddressableComponent(self, node: 'AddressableNode') -> Optional[WalkerAction]:
@@ -157,7 +157,7 @@ class DecodeLogicGenerator(RDLForLoopGenerator):
             # Is an external block
             addr_str = self._get_address_str(node)
             strb = self.addr_decode.get_external_block_access_strobe(node)
-            rhs = f"cpuif_req_masked & (cpuif_addr >= {addr_str}) & (cpuif_addr <= {addr_str} + 'h{(node.size - 1):x})"
+            rhs = f"cpuif_req_masked & (cpuif_addr >= {addr_str}) & (cpuif_addr <= {addr_str} + {get_sv_int(node.size - 1)})"
             self.add_content(f"{strb} = {rhs};")
             self.add_content(f"is_external |= {rhs};")
             return WalkerAction.SkipDescendants
@@ -166,9 +166,9 @@ class DecodeLogicGenerator(RDLForLoopGenerator):
 
 
     def _get_address_str(self, node: 'AddressableNode', subword_offset: int=0) -> str:
-        a = f"'h{(node.raw_absolute_address - self.addr_decode.top_node.raw_absolute_address + subword_offset):x}"
+        a = get_sv_int(node.raw_absolute_address - self.addr_decode.top_node.raw_absolute_address + subword_offset)
         for i, stride in enumerate(self._array_stride_stack):
-            a += f" + i{i}*'h{stride:x}"
+            a += f" + i{i}*{get_sv_int(stride)}"
         return a
 
 

src/peakrdl_regblock/dereferencer.py

@@ -2,6 +2,8 @@ from typing import TYPE_CHECKING, Union, Optional
 from systemrdl.node import AddrmapNode, FieldNode, SignalNode, RegNode, AddressableNode
 from systemrdl.rdltypes import PropertyReference
 
+from .utils import get_sv_int
+
 if TYPE_CHECKING:
     from .exporter import RegblockExporter, DesignState
     from .hwif import Hwif
@@ -48,7 +50,7 @@ class Dereferencer:
         """
         if isinstance(obj, int):
             # Is a simple scalar value
-            return f"'h{obj:x}"
+            return get_sv_int(obj)
 
         if isinstance(obj, FieldNode):
             if obj.implements_storage:

src/peakrdl_regblock/hwif/generators.py

@@ -5,6 +5,7 @@ from systemrdl.walker import WalkerAction
 
 from ..struct_generator import RDLFlatStructGenerator
 from ..identifier_filter import kw_filter as kwf
+from ..utils import get_sv_int
 
 if TYPE_CHECKING:
     from systemrdl.node import Node, SignalNode, AddressableNode, RegfileNode
@@ -295,7 +296,7 @@ class EnumGenerator:
 
         lines = []
         for enum_member in user_enum:
-            lines.append(f"    {prefix}__{enum_member.name} = 'd{enum_member.value}")
+            lines.append(f"    {prefix}__{enum_member.name} = {get_sv_int(enum_member.value)}")
 
         return (
             "typedef enum {\n"

src/peakrdl_regblock/utils.py

@@ -64,3 +64,11 @@ def ref_is_internal(top_node: AddrmapNode, ref: Union[Node, PropertyReference])
     # A root signal was referenced, which dodged the top addrmap
     # This is considerd internal for this exporter
     return True
+
+def get_sv_int(n: int) -> str:
+    if n.bit_length() <= 32:
+        return f"'h{n:x}"
+    else:
+        # SV standard only enforces that unsized literals shall be at least 32-bits
+        # To support larger literals, they need to be sized explicitly
+        return f"{n.bit_length()}'h{n:x}"