diff --git a/.gitignore b/.gitignore index 6c730b9..79b5899 100644 --- a/.gitignore +++ b/.gitignore @@ -9,6 +9,7 @@ **/transcript **/*.log **/*.pb +**/.Xil build/ dist/ diff --git a/peakrdl/regblock/cpuif/apb3/__init__.py b/peakrdl/regblock/cpuif/apb3/__init__.py index 6674d6c..1b79ff0 100644 --- a/peakrdl/regblock/cpuif/apb3/__init__.py +++ b/peakrdl/regblock/cpuif/apb3/__init__.py @@ -1,7 +1,7 @@ from ..base import CpuifBase class APB3_Cpuif(CpuifBase): - template_path = "cpuif/apb3/apb3_tmpl.sv" + template_path = "apb3_tmpl.sv" @property def port_declaration(self) -> str: diff --git a/peakrdl/regblock/cpuif/axi4lite/__init__.py b/peakrdl/regblock/cpuif/axi4lite/__init__.py index a882541..222aa9f 100644 --- a/peakrdl/regblock/cpuif/axi4lite/__init__.py +++ b/peakrdl/regblock/cpuif/axi4lite/__init__.py @@ -1,7 +1,7 @@ from ..base import CpuifBase class AXI4Lite_Cpuif(CpuifBase): - template_path = "cpuif/axi4lite/axi4lite_tmpl.sv" + template_path = "axi4lite_tmpl.sv" @property def port_declaration(self) -> str: diff --git a/peakrdl/regblock/cpuif/base.py b/peakrdl/regblock/cpuif/base.py index 967ef35..869ad51 100644 --- a/peakrdl/regblock/cpuif/base.py +++ b/peakrdl/regblock/cpuif/base.py @@ -1,4 +1,8 @@ from typing import TYPE_CHECKING, Optional +import inspect +import os + +import jinja2 as jj from ..utils import get_always_ff_event, clog2, is_pow2 @@ -7,6 +11,8 @@ if TYPE_CHECKING: from systemrdl import SignalNode class CpuifBase: + + # Path is relative to class that defines it template_path = "" def __init__(self, exp:'RegblockExporter', cpuif_reset:Optional['SignalNode'], data_width:int=32, addr_width:int=32): @@ -20,6 +26,13 @@ class CpuifBase: raise NotImplementedError() def get_implementation(self) -> str: + class_dir = os.path.dirname(inspect.getfile(self.__class__)) + loader = jj.FileSystemLoader(class_dir) + jj_env = jj.Environment( + loader=loader, + undefined=jj.StrictUndefined, + ) + context = { "cpuif": self, "get_always_ff_event": lambda resetsignal : get_always_ff_event(self.exp.dereferencer, resetsignal), @@ -28,5 +41,5 @@ class CpuifBase: "is_pow2": is_pow2, } - template = self.exp.jj_env.get_template(self.template_path) + template = jj_env.get_template(self.template_path) return template.render(context) diff --git a/peakrdl/regblock/cpuif/passthrough/__init__.py b/peakrdl/regblock/cpuif/passthrough/__init__.py index 975a324..cfbeeee 100644 --- a/peakrdl/regblock/cpuif/passthrough/__init__.py +++ b/peakrdl/regblock/cpuif/passthrough/__init__.py @@ -1,7 +1,7 @@ from ..base import CpuifBase class PassthroughCpuif(CpuifBase): - template_path = "cpuif/passthrough/passthrough_tmpl.sv" + template_path = "passthrough_tmpl.sv" @property def port_declaration(self) -> str: diff --git a/peakrdl/regblock/exporter.py b/peakrdl/regblock/exporter.py index e4e075e..bd5392d 100644 --- a/peakrdl/regblock/exporter.py +++ b/peakrdl/regblock/exporter.py @@ -17,8 +17,6 @@ from .scan_design import DesignScanner class RegblockExporter: def __init__(self, **kwargs) -> None: - user_template_dir = kwargs.pop("user_template_dir", None) - # Check for stray kwargs if kwargs: raise TypeError("got an unexpected keyword argument '%s'" % list(kwargs.keys())[0]) @@ -34,22 +32,12 @@ class RegblockExporter: self.min_read_latency = 0 self.min_write_latency = 0 - if user_template_dir: - loader = jj.ChoiceLoader([ - jj.FileSystemLoader(user_template_dir), - jj.FileSystemLoader(os.path.dirname(__file__)), - jj.PrefixLoader({ - 'user': jj.FileSystemLoader(user_template_dir), - 'base': jj.FileSystemLoader(os.path.dirname(__file__)), - }, delimiter=":") - ]) - else: - loader = jj.ChoiceLoader([ - jj.FileSystemLoader(os.path.dirname(__file__)), - jj.PrefixLoader({ - 'base': jj.FileSystemLoader(os.path.dirname(__file__)), - }, delimiter=":") - ]) + loader = jj.ChoiceLoader([ + jj.FileSystemLoader(os.path.dirname(__file__)), + jj.PrefixLoader({ + 'base': jj.FileSystemLoader(os.path.dirname(__file__)), + }, delimiter=":") + ]) self.jj_env = jj.Environment( loader=loader, diff --git a/test/README.md b/test/README.md index 6f01098..a656e71 100644 --- a/test/README.md +++ b/test/README.md @@ -11,6 +11,20 @@ https://fpgasoftware.intel.com/ and is sufficient to run unit tests. You will ne to generate a free license file to unlock the software: https://licensing.intel.com/psg/s/sales-signup-evaluationlicenses + +## Vivado (optional) + +To run synthesis tests, Vivado needs to be installed and visible via the PATH environment variable. + +Vivado can be downloaded for free from: https://www.xilinx.com/support/download.html + +To skip synthesis tests, export the following environment variable: +```bash +export SKIP_SYNTH_TESTS=1 +``` + + + ## Python Packages Install dependencies required for running tests @@ -18,6 +32,8 @@ Install dependencies required for running tests python3 -m pip install test/requirements.txt ``` + + # Running tests Tests can be launched from the test directory using `pytest`. @@ -36,6 +52,7 @@ pytest ``` + # Test organization The goal for this test infrastructure is to make it easy to add small-standalone diff --git a/test/lib/regblock_testcase.py b/test/lib/base_testcase.py similarity index 51% rename from test/lib/regblock_testcase.py rename to test/lib/base_testcase.py index 6466b4b..07b1c71 100644 --- a/test/lib/regblock_testcase.py +++ b/test/lib/base_testcase.py @@ -7,19 +7,14 @@ import inspect import pathlib import pytest -import jinja2 as jj from systemrdl import RDLCompiler -from .sv_line_anchor import SVLineAnchor - from peakrdl.regblock import RegblockExporter from .cpuifs.base import CpuifTestMode from .cpuifs.apb3 import APB3 -from .simulators.questa import Questa - -class RegblockTestCase(unittest.TestCase): +class BaseTestCase(unittest.TestCase): #: Path to the testcase's RDL file. #: Relative to the testcase's dir. If unset, the first RDL file found in the #: testcase dir will be used @@ -39,14 +34,11 @@ class RegblockTestCase(unittest.TestCase): retime_read_fanin = False retime_read_response = False - #: Abort test if it exceeds this number of clock cycles - timeout_clk_cycles = 5000 - - simulator_cls = Questa - #: this gets auto-loaded via the _load_request autouse fixture request = None # type: pytest.FixtureRequest + exporter = RegblockExporter() + @pytest.fixture(autouse=True) def _load_request(self, request): self.request = request @@ -57,10 +49,10 @@ class RegblockTestCase(unittest.TestCase): return class_dir @classmethod - def get_build_dir(cls) -> str: + def get_run_dir(cls) -> str: this_dir = cls.get_testcase_dir() - build_dir = os.path.join(this_dir, "run.out", cls.__name__) - return build_dir + run_dir = os.path.join(this_dir, "run.out", cls.__name__) + return run_dir @classmethod def _write_params(cls) -> None: @@ -68,7 +60,7 @@ class RegblockTestCase(unittest.TestCase): Write out the class parameters to a file so that it is easier to debug how a testcase was parameterized """ - path = os.path.join(cls.get_build_dir(), "params.txt") + path = os.path.join(cls.get_run_dir(), "params.txt") with open(path, 'w') as f: for k, v in cls.__dict__.items(): @@ -78,7 +70,7 @@ class RegblockTestCase(unittest.TestCase): @classmethod - def _export_regblock(cls) -> RegblockExporter: + def _export_regblock(cls): """ Call the peakrdl.regblock exporter to generate the DUT """ @@ -94,10 +86,9 @@ class RegblockTestCase(unittest.TestCase): rdlc.compile_file(rdl_file) root = rdlc.elaborate(cls.rdl_elab_target, "regblock", cls.rdl_elab_params) - exporter = RegblockExporter() - exporter.export( + cls.exporter.export( root, - cls.get_build_dir(), + cls.get_run_dir(), module_name="regblock", package_name="regblock_pkg", cpuif_cls=cls.cpuif.cpuif_cls, @@ -105,88 +96,26 @@ class RegblockTestCase(unittest.TestCase): retime_read_response=cls.retime_read_response, ) - return exporter - - @classmethod - def _generate_tb(cls, exporter: RegblockExporter): - """ - Render the testbench template into actual tb.sv - """ - template_root_path = os.path.join(os.path.dirname(__file__), "..") - loader = jj.FileSystemLoader( - template_root_path - ) - jj_env = jj.Environment( - loader=loader, - undefined=jj.StrictUndefined, - extensions=[SVLineAnchor], - ) - - context = { - "cls": cls, - "exporter": exporter, - } - - # template path needs to be relative to the Jinja loader root - template_path = os.path.join(cls.get_testcase_dir(), "tb_template.sv") - template_path = os.path.relpath(template_path, template_root_path) - template = jj_env.get_template(template_path) - - output_path = os.path.join(cls.get_build_dir(), "tb.sv") - stream = template.stream(context) - stream.dump(output_path) - - @classmethod def setUpClass(cls): # Create fresh build dir - build_dir = cls.get_build_dir() - if os.path.exists(build_dir): - shutil.rmtree(build_dir) - pathlib.Path(build_dir).mkdir(parents=True, exist_ok=True) + run_dir = cls.get_run_dir() + if os.path.exists(run_dir): + shutil.rmtree(run_dir) + pathlib.Path(run_dir).mkdir(parents=True, exist_ok=True) cls._write_params() # Convert testcase RDL file --> SV - exporter = cls._export_regblock() - - # Create testbench from template - cls._generate_tb(exporter) - - simulator = cls.simulator_cls(testcase_cls=cls) - - # cd into the build directory - cwd = os.getcwd() - os.chdir(cls.get_build_dir()) - try: - simulator.compile() - finally: - # cd back - os.chdir(cwd) + cls._export_regblock() def setUp(self) -> None: - # cd into the build directory + # cd into the run directory self.original_cwd = os.getcwd() - os.chdir(self.get_build_dir()) + os.chdir(self.get_run_dir()) def run_test(self, plusargs:List[str] = None) -> None: simulator = self.simulator_cls(testcase_cls_inst=self) simulator.run(plusargs) - - - def tearDown(self) -> None: - # cd back - os.chdir(self.original_cwd) - - - def assertSimLogPass(self, path: str): - self.assertTrue(os.path.isfile(path)) - - with open(path, encoding="utf-8") as f: - for line in f: - if line.startswith("# ** Error"): - self.fail(line) - elif line.startswith("# ** Fatal"): - self.fail(line) diff --git a/test/lib/cpuifs/apb3/__init__.py b/test/lib/cpuifs/apb3/__init__.py index e9d9ceb..3a3a9a5 100644 --- a/test/lib/cpuifs/apb3/__init__.py +++ b/test/lib/cpuifs/apb3/__init__.py @@ -4,6 +4,9 @@ from peakrdl.regblock.cpuif.apb3 import APB3_Cpuif, APB3_Cpuif_flattened class APB3(CpuifTestMode): cpuif_cls = APB3_Cpuif + rtl_files = [ + "apb3_intf.sv", + ] tb_files = [ "apb3_intf.sv", "apb3_intf_driver.sv", @@ -12,3 +15,4 @@ class APB3(CpuifTestMode): class FlatAPB3(APB3): cpuif_cls = APB3_Cpuif_flattened + rtl_files = [] diff --git a/test/lib/cpuifs/axi4lite/__init__.py b/test/lib/cpuifs/axi4lite/__init__.py index 6fc236c..08fc3bf 100644 --- a/test/lib/cpuifs/axi4lite/__init__.py +++ b/test/lib/cpuifs/axi4lite/__init__.py @@ -4,6 +4,9 @@ from peakrdl.regblock.cpuif.axi4lite import AXI4Lite_Cpuif, AXI4Lite_Cpuif_flatt class AXI4Lite(CpuifTestMode): cpuif_cls = AXI4Lite_Cpuif + rtl_files = [ + "axi4lite_intf.sv", + ] tb_files = [ "axi4lite_intf.sv", "axi4lite_intf_driver.sv", @@ -12,3 +15,4 @@ class AXI4Lite(CpuifTestMode): class FlatAXI4Lite(AXI4Lite): cpuif_cls = AXI4Lite_Cpuif_flattened + rtl_files = [] diff --git a/test/lib/cpuifs/base.py b/test/lib/cpuifs/base.py index 52280bb..0adba78 100644 --- a/test/lib/cpuifs/base.py +++ b/test/lib/cpuifs/base.py @@ -10,35 +10,42 @@ from ..sv_line_anchor import SVLineAnchor if TYPE_CHECKING: from peakrdl.regblock import RegblockExporter - from ..regblock_testcase import RegblockTestCase + from ..sim_testcase import SimTestCase class CpuifTestMode: cpuif_cls = None # type: CpuifBase + + # Files required by the DUT + rtl_files = [] # type: List[str] + + # Files required by the sim testbench tb_files = [] # type: List[str] + tb_template = "" - def get_tb_files(self) -> List[str]: + def _translate_paths(self, files: List[str]) -> List[str]: class_dir = os.path.dirname(inspect.getfile(self.__class__)) cwd = os.getcwd() - tb_files = [] - for file in self.tb_files: + new_files = [] + for file in files: relpath = os.path.relpath( os.path.join(class_dir, file), cwd ) - tb_files.append(relpath) - return tb_files + if relpath not in new_files: + new_files.append(relpath) + return new_files + def get_sim_files(self) -> List[str]: + return self._translate_paths(self.rtl_files + self.tb_files) - def get_tb_inst(self, tb_cls: 'RegblockTestCase', exporter: 'RegblockExporter') -> str: + def get_synth_files(self) -> List[str]: + return self._translate_paths(self.rtl_files) - # For consistency, make the template root path relative to the test dir - template_root_path = os.path.join(os.path.dirname(__file__), "../..") - - loader = jj.FileSystemLoader( - template_root_path - ) + def get_tb_inst(self, tb_cls: 'SimTestCase', exporter: 'RegblockExporter') -> str: + class_dir = os.path.dirname(inspect.getfile(self.__class__)) + loader = jj.FileSystemLoader(class_dir) jj_env = jj.Environment( loader=loader, undefined=jj.StrictUndefined, @@ -52,11 +59,6 @@ class CpuifTestMode: "type": type, } - # template paths are relative to their class. - # transform to be relative to the root path - class_dir = os.path.dirname(inspect.getfile(self.__class__)) - template_local_path = os.path.join(class_dir, self.tb_template) - template_path = os.path.relpath(template_local_path, template_root_path) - template = jj_env.get_template(template_path) + template = jj_env.get_template(self.tb_template) return template.render(context) diff --git a/test/lib/cpuifs/passthrough/__init__.py b/test/lib/cpuifs/passthrough/__init__.py index 4883d70..a157462 100644 --- a/test/lib/cpuifs/passthrough/__init__.py +++ b/test/lib/cpuifs/passthrough/__init__.py @@ -4,6 +4,7 @@ from peakrdl.regblock.cpuif.passthrough import PassthroughCpuif class Passthrough(CpuifTestMode): cpuif_cls = PassthroughCpuif + rtl_files = [] tb_files = [ "passthrough_driver.sv", ] diff --git a/test/lib/sim_testcase.py b/test/lib/sim_testcase.py new file mode 100644 index 0000000..d7c40e0 --- /dev/null +++ b/test/lib/sim_testcase.py @@ -0,0 +1,69 @@ +from typing import List +import os +import jinja2 as jj + +from .sv_line_anchor import SVLineAnchor + +from .simulators.questa import Questa + +from .base_testcase import BaseTestCase + + +class SimTestCase(BaseTestCase): + #: Abort test if it exceeds this number of clock cycles + timeout_clk_cycles = 5000 + + simulator_cls = Questa + + @classmethod + def _generate_tb(cls): + """ + Render the testbench template into actual tb.sv + """ + template_root_path = os.path.join(os.path.dirname(__file__), "..") + loader = jj.FileSystemLoader( + template_root_path + ) + jj_env = jj.Environment( + loader=loader, + undefined=jj.StrictUndefined, + extensions=[SVLineAnchor], + ) + + context = { + "cls": cls, + "exporter": cls.exporter, + } + + # template path needs to be relative to the Jinja loader root + template_path = os.path.join(cls.get_testcase_dir(), "tb_template.sv") + template_path = os.path.relpath(template_path, template_root_path) + template = jj_env.get_template(template_path) + + output_path = os.path.join(cls.get_run_dir(), "tb.sv") + stream = template.stream(context) + stream.dump(output_path) + + + @classmethod + def setUpClass(cls): + super().setUpClass() + + # Create testbench from template + cls._generate_tb() + + simulator = cls.simulator_cls(testcase_cls=cls) + + # cd into the build directory + cwd = os.getcwd() + os.chdir(cls.get_run_dir()) + try: + simulator.compile() + finally: + # cd back + os.chdir(cwd) + + + def run_test(self, plusargs:List[str] = None) -> None: + simulator = self.simulator_cls(testcase_cls_inst=self) + simulator.run(plusargs) diff --git a/test/lib/simulators/__init__.py b/test/lib/simulators/__init__.py index fd4014d..975f2a1 100644 --- a/test/lib/simulators/__init__.py +++ b/test/lib/simulators/__init__.py @@ -1,18 +1,18 @@ from typing import Type, TYPE_CHECKING, List if TYPE_CHECKING: - from ..regblock_testcase import RegblockTestCase + from ..sim_testcase import SimTestCase class Simulator: - def __init__(self, testcase_cls: 'Type[RegblockTestCase]' = None, testcase_cls_inst: 'RegblockTestCase' = None) -> None: + def __init__(self, testcase_cls: 'Type[SimTestCase]' = None, testcase_cls_inst: 'SimTestCase' = None) -> None: self.testcase_cls = testcase_cls self.testcase_cls_inst = testcase_cls_inst @property def tb_files(self) -> List[str]: files = [] - files.extend(self.testcase_cls.cpuif.get_tb_files()) + files.extend(self.testcase_cls.cpuif.get_sim_files()) files.append("regblock_pkg.sv") files.append("regblock.sv") files.append("tb.sv") diff --git a/test/lib/synth_testcase.py b/test/lib/synth_testcase.py new file mode 100644 index 0000000..cc56f0d --- /dev/null +++ b/test/lib/synth_testcase.py @@ -0,0 +1,36 @@ +from typing import List +import subprocess +import os + +import pytest + +from .base_testcase import BaseTestCase + +@pytest.mark.skipif(os.environ.get("SKIP_SYNTH_TESTS", False), reason="user skipped") +class SynthTestCase(BaseTestCase): + + def _get_synth_files(self) -> List[str]: + files = [] + files.extend(self.cpuif.get_synth_files()) + files.append("regblock_pkg.sv") + files.append("regblock.sv") + + return files + + + def run_synth(self) -> None: + script = os.path.join( + os.path.dirname(__file__), + "synthesis/vivado/run.tcl" + ) + + cmd = [ + "vivado", "-nojournal", "-notrace", + "-mode", "batch", + "-log", "out.log", + "-source", script, + "-tclargs" + ] + cmd.extend(self._get_synth_files()) + + subprocess.run(cmd, check=True) diff --git a/test/lib/synthesis/vivado/constr.xdc b/test/lib/synthesis/vivado/constr.xdc new file mode 100644 index 0000000..3c063c1 --- /dev/null +++ b/test/lib/synthesis/vivado/constr.xdc @@ -0,0 +1,8 @@ + +create_clock -period 10.000 -name clk [get_ports clk] + +set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports -filter {(DIRECTION == IN) && (NAME != clk)}] +set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports -filter {(DIRECTION == IN) && (NAME != clk)}] + +set_output_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports -filter {DIRECTION == OUT}] +set_output_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports -filter {DIRECTION == OUT}] diff --git a/test/lib/synthesis/vivado/run.tcl b/test/lib/synthesis/vivado/run.tcl new file mode 100644 index 0000000..ba8ae54 --- /dev/null +++ b/test/lib/synthesis/vivado/run.tcl @@ -0,0 +1,34 @@ +set this_dir [file dirname [file normalize [info script]]] +set files $argv + + +# Multi-driven +set_msg_config -id {[Synth 8-6858]} -new_severity "ERROR" +set_msg_config -id {[Synth 8-6859]} -new_severity "ERROR" + +# Implicit net +set_msg_config -id {[Synth 8-992]} -new_severity "ERROR" + +# Non-combo always_comb +set_msg_config -id {[Synth 8-87]} -new_severity "ERROR" + +# Latch +set_msg_config -id {[Synth 8-327]} -new_severity "ERROR" + +# Timing loop +set_msg_config -id {[Synth 8-295]} -new_severity "ERROR" + +# Promote all critical warnings to errors +set_msg_config -severity {CRITICAL WARNING} -new_severity "ERROR" + + +set_part xczu7eg-ffvf1517-2-i +read_verilog -sv $files +read_xdc $this_dir/constr.xdc +synth_design -top regblock -mode out_of_context + +#write_checkpoint -force synth.dcp + +if {[get_msg_config -count -severity {CRITICAL WARNING}] || [get_msg_config -count -severity ERROR]} { + error "Encountered errors" +} diff --git a/test/test_bitwise_reduce/testcase.py b/test/test_bitwise_reduce/testcase.py index b458d3c..835b5ef 100644 --- a/test/test_bitwise_reduce/testcase.py +++ b/test/test_bitwise_reduce/testcase.py @@ -1,5 +1,5 @@ -from ..lib.regblock_testcase import RegblockTestCase +from ..lib.sim_testcase import SimTestCase -class Test(RegblockTestCase): +class Test(SimTestCase): def test_dut(self): self.run_test() diff --git a/test/test_counter_basics/testcase.py b/test/test_counter_basics/testcase.py index b458d3c..835b5ef 100644 --- a/test/test_counter_basics/testcase.py +++ b/test/test_counter_basics/testcase.py @@ -1,5 +1,5 @@ -from ..lib.regblock_testcase import RegblockTestCase +from ..lib.sim_testcase import SimTestCase -class Test(RegblockTestCase): +class Test(SimTestCase): def test_dut(self): self.run_test() diff --git a/test/test_counter_saturate/testcase.py b/test/test_counter_saturate/testcase.py index b458d3c..835b5ef 100644 --- a/test/test_counter_saturate/testcase.py +++ b/test/test_counter_saturate/testcase.py @@ -1,5 +1,5 @@ -from ..lib.regblock_testcase import RegblockTestCase +from ..lib.sim_testcase import SimTestCase -class Test(RegblockTestCase): +class Test(SimTestCase): def test_dut(self): self.run_test() diff --git a/test/test_counter_threshold/testcase.py b/test/test_counter_threshold/testcase.py index b458d3c..835b5ef 100644 --- a/test/test_counter_threshold/testcase.py +++ b/test/test_counter_threshold/testcase.py @@ -1,5 +1,5 @@ -from ..lib.regblock_testcase import RegblockTestCase +from ..lib.sim_testcase import SimTestCase -class Test(RegblockTestCase): +class Test(SimTestCase): def test_dut(self): self.run_test() diff --git a/test/test_field_types/testcase.py b/test/test_field_types/testcase.py index b458d3c..835b5ef 100644 --- a/test/test_field_types/testcase.py +++ b/test/test_field_types/testcase.py @@ -1,5 +1,5 @@ -from ..lib.regblock_testcase import RegblockTestCase +from ..lib.sim_testcase import SimTestCase -class Test(RegblockTestCase): +class Test(SimTestCase): def test_dut(self): self.run_test() diff --git a/test/test_hw_access/testcase.py b/test/test_hw_access/testcase.py index b458d3c..835b5ef 100644 --- a/test/test_hw_access/testcase.py +++ b/test/test_hw_access/testcase.py @@ -1,5 +1,5 @@ -from ..lib.regblock_testcase import RegblockTestCase +from ..lib.sim_testcase import SimTestCase -class Test(RegblockTestCase): +class Test(SimTestCase): def test_dut(self): self.run_test() diff --git a/test/test_interrupts/testcase.py b/test/test_interrupts/testcase.py index b458d3c..835b5ef 100644 --- a/test/test_interrupts/testcase.py +++ b/test/test_interrupts/testcase.py @@ -1,5 +1,5 @@ -from ..lib.regblock_testcase import RegblockTestCase +from ..lib.sim_testcase import SimTestCase -class Test(RegblockTestCase): +class Test(SimTestCase): def test_dut(self): self.run_test() diff --git a/test/test_onread_onwrite/testcase.py b/test/test_onread_onwrite/testcase.py index b458d3c..835b5ef 100644 --- a/test/test_onread_onwrite/testcase.py +++ b/test/test_onread_onwrite/testcase.py @@ -1,5 +1,5 @@ -from ..lib.regblock_testcase import RegblockTestCase +from ..lib.sim_testcase import SimTestCase -class Test(RegblockTestCase): +class Test(SimTestCase): def test_dut(self): self.run_test() diff --git a/test/test_pipelined_cpuif/testcase.py b/test/test_pipelined_cpuif/testcase.py index a0e39d0..422861b 100644 --- a/test/test_pipelined_cpuif/testcase.py +++ b/test/test_pipelined_cpuif/testcase.py @@ -1,9 +1,9 @@ from parameterized import parameterized_class -from ..lib.regblock_testcase import RegblockTestCase +from ..lib.sim_testcase import SimTestCase from ..lib.test_params import TEST_PARAMS @parameterized_class(TEST_PARAMS) -class Test(RegblockTestCase): +class Test(SimTestCase): def test_dut(self): self.run_test() diff --git a/test/test_read_fanin/testcase.py b/test/test_read_fanin/testcase.py index 6b3d4f8..2398536 100644 --- a/test/test_read_fanin/testcase.py +++ b/test/test_read_fanin/testcase.py @@ -1,6 +1,6 @@ from parameterized import parameterized_class -from ..lib.regblock_testcase import RegblockTestCase +from ..lib.sim_testcase import SimTestCase from ..lib.test_params import get_permutations @@ -8,7 +8,7 @@ PARAMS = get_permutations({ "regwidth" : [8, 16, 32, 64], }) @parameterized_class(PARAMS) -class TestFanin(RegblockTestCase): +class TestFanin(SimTestCase): retime_read_fanin = False n_regs = 20 regwidth = 32 diff --git a/test/test_reset_signals/testcase.py b/test/test_reset_signals/testcase.py index b458d3c..835b5ef 100644 --- a/test/test_reset_signals/testcase.py +++ b/test/test_reset_signals/testcase.py @@ -1,5 +1,5 @@ -from ..lib.regblock_testcase import RegblockTestCase +from ..lib.sim_testcase import SimTestCase -class Test(RegblockTestCase): +class Test(SimTestCase): def test_dut(self): self.run_test() diff --git a/test/test_singlepulse/testcase.py b/test/test_singlepulse/testcase.py index b458d3c..835b5ef 100644 --- a/test/test_singlepulse/testcase.py +++ b/test/test_singlepulse/testcase.py @@ -1,5 +1,5 @@ -from ..lib.regblock_testcase import RegblockTestCase +from ..lib.sim_testcase import SimTestCase -class Test(RegblockTestCase): +class Test(SimTestCase): def test_dut(self): self.run_test() diff --git a/test/test_structural_sw_rw/testcase.py b/test/test_structural_sw_rw/testcase.py index a0e39d0..09a1eaa 100644 --- a/test/test_structural_sw_rw/testcase.py +++ b/test/test_structural_sw_rw/testcase.py @@ -1,9 +1,15 @@ from parameterized import parameterized_class -from ..lib.regblock_testcase import RegblockTestCase +from ..lib.sim_testcase import SimTestCase +from ..lib.synth_testcase import SynthTestCase from ..lib.test_params import TEST_PARAMS @parameterized_class(TEST_PARAMS) -class Test(RegblockTestCase): +class Test(SimTestCase): def test_dut(self): self.run_test() + +@parameterized_class(TEST_PARAMS) +class TestSynth(SynthTestCase): + def test_dut(self): + self.run_synth() diff --git a/test/test_swacc_swmod/testcase.py b/test/test_swacc_swmod/testcase.py index b458d3c..835b5ef 100644 --- a/test/test_swacc_swmod/testcase.py +++ b/test/test_swacc_swmod/testcase.py @@ -1,5 +1,5 @@ -from ..lib.regblock_testcase import RegblockTestCase +from ..lib.sim_testcase import SimTestCase -class Test(RegblockTestCase): +class Test(SimTestCase): def test_dut(self): self.run_test() diff --git a/test/test_swwe/testcase.py b/test/test_swwe/testcase.py index b458d3c..835b5ef 100644 --- a/test/test_swwe/testcase.py +++ b/test/test_swwe/testcase.py @@ -1,5 +1,5 @@ -from ..lib.regblock_testcase import RegblockTestCase +from ..lib.sim_testcase import SimTestCase -class Test(RegblockTestCase): +class Test(SimTestCase): def test_dut(self): self.run_test()